Monolithic memory sense amplifier/bit driver

Claim 2

A circuit for differentially sensing an output signal from a memory storage cell when data in the cell is to be read comprising: a separate input means for the receipt of each of the signals to be differentially sensed; a separate shunt feedback amplifying means coupled to each of said separate input means for separately amplifying each of the signals to be sensed and current an output signal to be detected at a separate output terminal; current source means differentially coupling the shunt feedback amplifying means together so that current supplied to one of the shunt feedback amplifying means depends on the current supplied to the other shunt feedback amplifying means; and compensation means coupling the output terminals of both shunt amplifying means together for making potentials on said input means relatively independent of one another.

Claim 3

The circuit of claim 1 wherein each said shunt feedback amplifying means includes: a common emitter stage having a first transistor with its base coupled to an input means, its emitter coupled to the current source means and providing an output at its collector; an emitter follower stage with a second transistor having its base coupled to the collector of the first transistor and its emitter coupled to the output terminal; and resistive feedback means coupling the base of the first transistor to the eMitter of the second transistor.

Claim 4

The circuit of claim 2 wherein said compensation means includes two resistive elements coupled in series between the output terminals of said shunt feedback amplifying means and a third resistive element coupling that point common to both said resistive elements to a reference potential.

Claim 5

The circuit of claim 3 including: a separate transistor coupling each of said inputs means to a reference potential when it is conducting; a first current switch circuit having transistors with their collectors coupled to the base of the first of the separate transistors and their emitters coupled to a first current source to bias the first of the separate transistors nonconducting when any one of the mentioned transistors in the first current switch circuit are conducting; a second current switch circuit having their collectors coupled to the base of the second of the separate transistors and their emitters coupled to a second common current source to bias the second of the separate transistors nonconducting when any of the mentioned transistors in the second current switch circuit are conducting; a cross-coupling transistor with its emitter coupled to the first current source and its collector coupled to the base of the second of the separate transistors so that this cross-coupling transistor conducts while the mentioned transistors in the first current switch circuit are all biased nonconducting to bias the second of the separate transistors off; and means for biasing the separate transistors on while they are not held off by the current switch circuits whereby a data signal need be supplied only to the first of the current switch circuit.

Claim 6

A bit driver circuit for controlling the potential on two bit lines comprising: a separate transistor coupling each of the bit lines to a reference potential when it is conducting; a first current switch circuit having transistors with their collectors coupled to the base of the first of the separate transistors and their emitters coupled to a first current source to bias the first of the separate transistors nonconducting when any one of the mentioned transistors in this first current switch circuit are conducting; a second current switch circuit having their collectors coupled to the base of the second of the separate transistors and their emitters coupled to a second common current source to bias the first of the separate transistors nonconducting when any of the mentioned transistors in the second current switch circuit are conducting; a cross-coupling transistor with its emitter coupled to the first current source and its collector coupled to the base of the second of the separate transistors so that this crosscoupling transistor conducts while the mentioned transistors in the first current switch circuit are all biased nonconducting to bias the second of the separate transistors off; and means for biasing the separate transistors on while they are not held off by the current switch circuits whereby a data signal need be supplied only to the first of the current switch circuits.

Claim 7

A bit driver circuit for controlling the potential on two bit lines comprising: a separate transistor coupling each of the bit lines to a reference potential when it is conducting; a first current switch circuit having transistors with their collectors coupled to the base of the first of the separate transistors and their emitters coupled to a first current source to bias the first of the separate transistors nonconducting when any one of the mentioned transistors in this first current switch circuit are conducting; a second current switch circuit having their collectors coupled to the base of the second of the separate transistors and their emitters coupled to a second common current source to bias the first of the separate transistors nonconducting when any of the mentioned transistors in the second current switch circuit are conducting; a cross-coupling transistor with its emitter coupled to the first current source and its collector coupled to the base of the second of the separate transistors so that this crosscoupling transistor conducts while the mentioned transistors in the first current switch circuit are all biased nonconducting to bias the second of the separate transistors off; and means for biasing the separate transistors on while they are not held off by the current switch circuits whereby a data signal need be supplied only to the first of the current switch circuits.