US4367538A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1981-02-20
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Granted: 1983-01-04
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Expires: 2001-02-20
Abstract
Abstract A semiconductor memory device of an MOS static type comprising a current switching mechanism, such as depletion type transistors, arranged between a power supply and bit lines. The current switching mechanism is controlled by column selection signals and supplied a larger current to the bit lines during the selected mode than the non-selected mode.
Inventors
- 👤 Hiroshi Shimada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:58
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
173 words
A semiconductor memory device comprising: a first power supply; a plurality of word lines; a plurality of pairs of bit lines forming columns and being connected to said first power supply; a plurality of pairs of load means, each load means pair being connected between said first power supply and corresponding pairs of bit lines; a plurality of pairs of column selecting gates, for receiving column selection signals, each gate pair connected to a corresponding one of said pairs of bit lines and controlled by a column selection signal; a plurality of memory cells of a static memory type, each memory cell connected to a corresponding one of said word lines and to a corresponding one of said pairs of bit lines; and current switching means, connected between said first power supply and each of said pairs of bit lines and controlled according to said column selection signals, for supplying a larger current to a selected one of said pairs of bit lines than other pairs of bit lines which are not selected.
Claim 2
Dependent Claim
173 words
A semiconductor memory device comprising: a first power supply; a plurality of word lines; a plurality of pairs of bit lines forming columns and being connected to said first power supply; a plurality of pairs of load means, each load means pair being connected between said first power supply and corresponding pairs of bit lines; a plurality of pairs of column selecting gates, for receiving column selection signals, each gate pair connected to a corresponding one of said pairs of bit lines and controlled by a column selection signal; a plurality of memory cells of a static memory type, each memory cell connected to a corresponding one of said word lines and to a corresponding one of said pairs of bit lines; and current switching means, connected between said first power supply and each of said pairs of bit lines and controlled according to said column selection signals, for supplying a larger current to a selected one of said pairs of bit lines than other pairs of bit lines which are not selected.
Claim 3
Dependent Claim
41 words
A device as set forth in claim 1, wherein said current switching means comprises a plurality of pairs of MOS transistors of a depletion type, each MOS transistor pair being controlled according to a corresponding one of said column selection signals.
Claim 4
Dependent Claim
121 words
A device as set forth in claim 1, wherein each of said memory cells of a static memory type comprises: first and second MOS transistors, each having a gate connected to a drain of the other, and a source connected to a second power supply; third and fourth MOS transistors, each having a drain connected to one of said bit lines associated with said memory cell, a source connected to one of the drains of said first and second MOS transistors, and a gate connected to said work line associated with said memory cell; and a pair of load resistors, each resistor being connected between said first power supply and one of the drains of said first and second MOS transistors.
Claim 5
Dependent Claim
130 words
A device as set forth in claim 1, wherein each of said memory cells of a static memory type comprises: first and second MOS transistors, each having a gate connected to a drain of the other, and a source connected to a second power supply; third and fourth MOS transistors, each having a drain connected to one of said bit lines associated with said memory cell, a source connected to one of the drains of said first and second MOS transistors, and a gate connected to said word line associated with said memory cell; and fifth and sixth MOS transistors, each having a drain connected to a gate thereof and to said first power supply, and a source connected to one of the drains of said first and second transistors.
Claim 6
Dependent Claim
41 words
A device as set forth in claim 1, wherein said current switching means comprises a plurality of pairs of MOS transistors of an enhancement type, each MOS transistor pair being controlled according to a corresponding one of said column selection signals.
References Cited (Backward Citations)
US4327424A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-01-03 | 1986-07-05 | 1987-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-01-03 | 1990-07-05 | 1991-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-01-03 | 1994-07-05 | 1995-01-04 | $7700.00 | Window Closed / Lapsed |