EP0055582A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Memory circuit having a decoder
Assignee: Fujitsu Ltd
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Filing: 1981-12-22
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Granted: —
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Expires: 2001-12-22
Abstract
Abstract A memory circuit having a decoder circuit (2) for receiving address signals (Ai, Ai) and generating word designating signals, said decoder circuit (2) having a plurality of decoder circuit blocks (0,1,2,3) and including means for receiving some of the address signals and generating signals designating one of the decoder circuit blocks, whereby the current flowing in each of said decoder circuit blocks is reduced as long as the blocks remain not designated.
Inventors
- 👤 Kazuo Tanimoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 22:49
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
70 words
1 . A memory circuit having a decoder, characterised in that said decoder is constituted by a plurality of blocks, each block being comprised of a plurality of decoding circuits for selecting word lines, and that said memory circuit comprises a means for selecting one of said plurality of blocks, whereby only one block to which a selected word line belongs will be rendered active in dependence upon address signals.
Claim 2
Dependent Claim
70 words
1 . A memory circuit having a decoder, characterised in that said decoder is constituted by a plurality of blocks, each block being comprised of a plurality of decoding circuits for selecting word lines, and that said memory circuit comprises a means for selecting one of said plurality of blocks, whereby only one block to which a selected word line belongs will be rendered active in dependence upon address signals.
Claim 3
Dependent Claim
20 words
A memory circuit having a decoder according to claim 1, wherein said means is operable to generate block designating signals.
Claim 4
Dependent Claim
60 words
A memory circuit having a decoder according to claim 2, wherein said decoding circuit comprises a plurality of MOS transistors which are connected in parallel to receive address signals at the gates, and an MOS transistor which is to receive said block designating signal at its gate and is connected between a voltage source and said plurality of MOS transistors.
References Cited (Backward Citations)
No citation records indexed.
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