Word line decoder and driver circuits for high density semiconductor memory

Claim 2

A narrow pitch CMOS word line decoder and driver circuit configuration for a semiconductor memory device comprising: a system clock circuit for generating clock pulses; a system voltage supply; a decoder circuit including at least one p-type transistor having a source electrode connected to said voltage supply, a gate electrode connected to gating signals and a drain electrode connected to a first node, and a plurality of n-type address switch transistors, each having a drain electrode connected to said first node, a source electrode connected to ground voltage and a gate electrode connected to a separate one of a plurality of input address signals; an inverter circuit including a pair of transistors, a first one of said pair of transistors having a source electrode connected to said voltage supply, a second one of said pair of transistors having a source electrode connected to ground voltage, said first and second inverter transistors having gate electrodes connected in common to said first node and drain electrodes connected in common to a second node; and means connecting said second node to word lines of said semiconductor memory device.

Claim 3

A narrow pitch CMOS word line decoder and driver circuit configuration according to claim 1 wherein said gating signals connected to said at least one p-type transistor are clock pulses generated by said system clock circuit.

Claim 4

A narrow pitch CMOS word line decoder and driver circuit configuration according to claim 1 wherein said gating signals connected to said at least one p-type transistor are input address signals.

Claim 5

A narrow pitch CMOS word line decoder and driver circuit configuration according to claim 2 wherein said means connecting said second node to said word lines includes a pair of push-pull transistors having drain electrode connected in common to each of said word lines, having gate electrodes connected in common to said second node, and a source electrode of one transistor of each of said pair of transistors being connected to row clock pulses from said system clock circuit.

Claim 6

A narrow pitch CMOS word line decoder and driver circuit configuration according to claim 2 wherein said means connecting said second node to said word lines includes a first pair of push-pull transistors having drain electrodes connected in common to a first word line; gate electrodes connected in common to said second node, the source electrode of one of said first pair of push-pull transistors connected to first row clock pulses from said system clock circuit and the source electrode of said other transistor of said first pair connected to ground voltage; and a second pair of push-pull transistors having drain electrodes connected in common to a second word line, gate electrodes connected in common to said second node, the source electrode of one of said second pair of push-pull transistors connected to second row clock pulses from said system clock circuit and the source electrode of said other transistor of said second pair connected to ground voltage.

Claim 7

A narrow pitch CMOS word line decoder and driver circuit configuration according to claim 2 wherein said means connecting said second node to said word lines includes a first pair of push-pull transistors having drain electrodes connected in common to a first word line; gate electrodes connected in common to said second node, the source electrode of one of said first pair of push-pull transistors connected to first row clock pulses from said system clock circuit and the source electrode of said other transistor of said first pair connected to said system voltage supply; and a second pair of push-pull transistors having drain electrodes connected in common to a second word line, gate electrodes connected in common to said second node, the source electrode of one of said second pair of push-pull transistors connected to second row clock pulses from said system clock circuit and the source electrode of said other transistor of said second pair connected to said system voltage supply.

Claim 8

A narrow pitch CMOS word line decoder and driver circuit configuration according to claim 4 further including a clamping transistor connected to each of said word lines and having a gate electrode connected to said system clock circuit and responsive to said clock pulses.

Claim 9

A narrow pitch CMOS word line decoder and driver circuit configuration according to claim 5 wherein further including a first clamping transistor connected to said first word line including a drain electrode connected to said first word line, a gate electrode connected to said second row clock pulses from said system clock circuit and a source electrode connected to ground voltage; and a second clamping transistor connected to said second word line including a drain electrode connected to said second word line, a gate electrode connected to said first row clock pulses from said system clock circuit and a source electrode connected to ground voltage.

Claim 10

A narrow pitch CMOS word line decoder and driver circuit configuration according to claim 5 wherein further including a first clamping transistor connected to said first word line including a drain electrode connected to said first word line, a gate electrode connected to said second row clock pulses from said system clock circuit and a source electrode connected to said ground system voltage supply; a second clamping transistor connected to said second word line including a drain electrode connected to said second word line, a gate electrode connected to said first row clock pulses from said system clock circuit and a source electrode connected to said system voltage supply.

Claim 11

In a narrow pitch CMOS word line decoder and driver circuit configuration for a semiconductor memory device characterized in having: a system clock circuit for generating clock pulses; a system voltage supply for producing a voltage V DD ; a decoder circuit including at least one p-type transistor having a source electrode connected to said voltage supply, a gate electrode connected to said clock circuit and responsive to line clock pulses therefrom and a drain electrode connected to a first node, and a plurality of n-type address switch transistors, each having a drain electrode connected to said first node, a source electrode connected to ground voltage and a gate electrode connected to a separate one of a plurality of input address signals; an inverter circuit including a pair of transistors, a first one of said pair of transistors having a source electrode connected to said voltage supply, a second one of said pair of transistors having a source electrode connected to ground voltage, said first and second inverter transistors having gate electrodes connected in common to said first node and drain electrodes connected in common to a second node; and means connecting said second node to said word lines includes a first pair of push-pull transistors having drain electrodes connected in common to a first word line; gate electrodes connected in common to said second node, the source electrode of one of said first pair of push-pull transistors connected to first row clock pulses from said system clock circuit and the source electrode of said other transistor of said first pair connected to ground voltage; and a second pair of push-pull transistors having drain electrodes connected in common to a second word line, gate electrodes connected in common to said second node, the source electrode of one of said second pair of push-pull transistors connected to second row clock pulses from said system clock circuit and the source electrode of said other transistor of said second pair connected to ground voltage; a method of providing decoder signals including the steps of: (1) initially biasing the input to said drain electrode of said p-type transistor, said plurality of input address signals and said second node at said VDD voltage and biasing said first and second row clock pulses, said first and second word lines and said first node at ground voltage: (2) causing one or more of said plurality of input address signals and said line clock pulse to go to ground voltage whereby said first node and one of said row clock pulses rises to voltage V DD ; (3) causing said second node to go to ground voltage thereby turning on one transistor in each of said first and second pairs of push-pull transistors; (4) causing one of said word lines to rise to voltage V DD and the other of said word line to remain at ground voltage; (5) and causing said line clock pulse to return to voltage V DD prior to said word line rising to voltage V DD in step 4.

Claim 12

In a narrow pitch CMOS word line decoder and driver circuit configuration for a semiconductor memory device characterized in having: a system clock circuit for generating clock pulses; a system voltage supply for producing a voltage V DD ; a decoder circuit including at least one p-type transistor having a source electrode connected to said voltage supply, a gate electrode connected to said clock circuit and responsive to line clock pulses therefrom and a drain electrode connected to a first node, and a plurality of n-type address switch transistors, each having a drain electrode connected to said first node, a source electrode connected to ground voltage and a gate electrode connected to a separate one of a plurality of input address signals; an inverter circuit including a pair of transistors, a first one of said pair of transistors having a source electrode connected to said voltage supply, a second one of said pair of transistors having a source electrode connected to ground voltage, said first and second inverter transistors having gate electrodes connected in common to said first node and drain electrodes connected in common to a second node; and means connecting said second node to said word lines includes a first pair of push-pull transistors having drain electrodes connected in common to a first word line; gate electrodes connected in common to said second node, the source electrode of one of said first pair of push-pull transistors connected to first row clock pulses from said system clock circuit and the source electrode of said other transistor of said first pair connected to ground voltage; and a second pair of push-pull transistors having drain electrodes connected in common to a second word line, gate electrodes connected in common to said second node, the source electrode of one of said second pair of push-pull transistors connected to second row clock pulses from said system clock circuit and the source electrode of said other transistor of said second pair connected to ground voltage; a method of providing decoder signals including the steps of: (1) initially biasing the input to said drain electrode of said p-type transistor, said plurality of input address signals and said second node at said VDD voltage and biasing said first and second row clock pulses, said first and second word lines and said first node at ground voltage: (2) causing one or more of said plurality of input address signals and said line clock pulse to go to ground voltage whereby said first node and one of said row clock pulses rises to voltage V DD ; (3) causing said second node to go to ground voltage thereby turning on one transistor in each of said first and second pairs of push-pull transistors; (4) causing one of said word lines to rise to voltage V DD and the other of said word line to remain at ground voltage; (5) and causing said line clock pulse to return to voltage V DD prior to said word line rising to voltage V DD in step 4.