Decoder circuit

Claim 2

In combination, at least two pairs of output terminals, a plurality of input terminals to which binary input signals and reference potential levels are to be supplied, at least one MOS device associated with each pair of output terminals and having its source and drain electrodes respectively connected thereto, a pair of MOS devices associated with each terminal of each pair of output terminals, each device of each such pair of devices having one of its source and drain electrodes connected to its associated terminal and the other one of its source and drain electrodes connected to one of said input terminals to which reference potential levels are to be supplied, and means connecting the gate electrodes of all of said devices to said input terminals to which binary input signals are to be supplied.

Claim 3

A combination as in claim 1 further including means connected to said input terminals for applying thereto binary input signals and reference potential levels.

Claim 4

In combination, at least first and second pairs of output terminals, at least one MOS transistor device associated with each pair of output terminals, means respectively connecting the source and drain electrodes of each MOS transistor device to its associated pair of output terminals, four additional MOS transistor devices associated with each pair of output terminals, means connecting one of the source and drain electrodes of each of two of said four MOS transistor devices to one of the associated pair of output terminals and connecting one of the source and drain electrodes of each of the other two MOS transistor devices to the other one of the associated pair of output terminals, a plurality of input terminals, and means respectively connecting said input terminals to the gate electrodes of said MOS deVices and to the other one of the source and drain electrodes of each of said four additional MOS devices connected to each pair of output terminals.

Claim 5

In combination, at least first and second pairs of output terminals, at least one MOS transistor device associated with each pair of output terminals, means respectively connecting the source and drain electrodes of each MOS transistor device to its associated pair of output terminals, four additional MOS transistor devices associated with each pair of output terminals, means connecting one of the source and drain electrodes of each of two of said four MOS transistor devices to one of the associated pair of output terminals and connecting one of the source and drain electrodes of each of the other two MOS transistor devices to the other one of the associated pair of output terminals, a plurality of input terminals, and means respectively connecting said input terminals to the gate electrodes of said MOS deVices and to the other one of the source and drain electrodes of each of said four additional MOS devices connected to each pair of output terminals.

Claim 6

A binary-to-one-out-of-N decoder circuit comprising N/2 sub-units each having two output lines emanating therefrom, where N 2n, n being any positive integer greater than one, x - 1 switching devices included in each of said sub-units and connected in parallel between the output lines emanating therefrom, where 2x N, four additional switching devices included in each of said sub-units and connected to the output lines emanating therefrom, two of the additional devices in each sub-unit each having one of its source and drain electrodes connected to one of the output lines emanating from the sub-unit and the other two of the additional devices in each sub-unit each having one of its source and drain electrodes connected to the other one of the output lines emanating from the sub-unit, and means for applying input signals to the respective devices included in said sub-units to establish one and only one of said output lines in a unique voltage condition.

Claim 7

A binary-to-one-out-of-N decoder circuit comprising N/2 sub-units each having two output lines emanating therefrom, where N 2n, n being any positive integer greater than one, x - 1 switching devices included in each of said sub-units and connected in parallel between the output lines emanating therefrom, where 2x N, four additional switching devices included in each of said sub-units and connected to the output lines emanating therefrom, two of the additional devices in each sub-unit each having one of its source and drain electrodes connected to one of the output lines emanating from the sub-unit and the other two of the additional devices in each sub-unit each having one of its source and drain electrodes connected to the other one of the output lines emanating from the sub-unit, and means for applying input signals to the respective devices included in said sub-units to establish one and only one of said output lines in a unique voltage condition.

Claim 8

A circuit as in claim 4 wherein each of said switching devices comprises an MOS transistor.

Claim 9

A binary-to-one-out-of-N decoder adapted to be fabricated on a single chip in integrated circuit form, where N 2n, n being any positive integer greater than one, said decoder comprising N/2 pairs of output terminals, at least one MOS transistor device having its source and drain electrodes respectively connected between each pair of output terminals, a set of four additional MOS transistor devices associated with each pair of output terminals, two of the additional devices in a set each having one of its source and drain electrodes connected to one terminal of the associated pair of output terminals and the other two of the additional devices in a set each having one of its source and drain electrodes connected to the other terminal of the associated pair of output terminals, and a plurality of input terminals connected to the gate electrodes of all said devices and to the other ones of the source and drain electrodes of each device of said sets of devices.

Claim 10

A binary-to-one-out-of-N decoder adapted to be fabricated on a single chip in integrated circuit form, where N 2n, n being any positive integer greater than one, said decoder comprising N/2 pairs of output terminals, at least one MOS transistor device having its source and drain electrodes respectively connected between each pair of output terminals, a set of four additional MOS transistor devices associated with each pair of output terminals, two of the additional devices in a set each having one of its source and drain electrodes connected to one terminal of the associated pair of output terminals and the other two of the additional devices in a set each having one of its source and drain electrodes connected to the other terminal of the associated pair of output terminals, and a plurality of input terminals connected to the gate electrodes of all said devices and to the other ones of the source and drain electrodes of each device of said sets of devices.