Fet binary to one out of n decoder

Claim 2

In combination, a. means for providing a first binary information signal on a first input lead; b. means responsive to a second binAry information signal for providing said second binary information signal on a second input lead and an inversion of said second binary information signal on a third input lead, the binary information signals each being capable of assuming either of two different voltage levels depending on the state of a bit of binary information being represented; c. a first field effect transistor having a gate and first and second controlled terminals; d. means for electrically connecting said first field effect transistor to said first and third input leads, said first controlled terminal being electrically connected directly to said first lead only and said gate being electrically connected directly to said third lead; e. an output conductor electrically connected directly to said second controlled terminal; f. a second field effect transistor having a gate, and first and second controlled terminals; g. means for electrically connecting said second field effect transistor to said second and third input leads, said first controlled terminal being electrically connected directly to said third lead and said gate being electrically connected directly to said second lead only; and h. means for electrically connecting said second controlled terminal of said first field effect transistor directly to said second controlled terminal of said second field effect transistor and to said output conductor.

Claim 3

The combination as defined in claim 1, also including: i. a third field effect transistor having a gate, and first and second controlled terminals; j. means for electrically connecting said third field effect transistor to said first and second input leads, said first controlled terminal being electrically connected directly to said first lead only and said gate being electrically connected directly to said second lead only; k. a second output conductor electrically connected directly to the second controlled terminal of said third field effect transistor; l. a fourth field effect transistor having a gate, and first and second controlled terminals; m. means for electrically connecting said fourth field effect transistor to said second and third input leads, said first controlled terminal being electrically connected directly to said second lead only and said gate being electrically connected directly to said third lead only; and n. means for electrically connecting said second controlled terminal of said third field effect transistor directly to said second controlled terminal of said fourth field effect transistor and to said second output conductor.

Claim 4

The combination as defined in claim 2 also including: first and second output capacitors connected between said first and second output conductors, respectively, and a low impedance point.

Claim 5

In combination, a. means responsive to a first binary information signal for providing said first binary information signal on a first input lead and an inversion of said first binary information signal on a second input lead so as to provide first complementary binary information signals on the first and second leads; b. means responsive to a second binary information signal for providing said second binary information signal on a third input lead and an inversion of said second binary information signal on a fourth input lead so as to provide second complementary binary information signals on the third and fourth leads; c. four pairs of field effect transistors, each field effect transistor having a gate and first and second controlled terminals; d. conductor means for electrically connecting a selected one of the four input leads directly to the gate of a first transistor from each pair, and for electrically connecting a selected one of the two leads associated with the other binary information signal directly to the first controlled terminal of each first transistor, the conductor means being arranged so that the four first transistors are connected in a patteRn wherein each first transistor has its gate and its first controlled terminal connected to a different combination of two of the input leads (other than the leads corresponding to each binary information signal and its inversion); e. conductor means for electrically connecting said second controlled terminal of each of said first field effect transistors in each of said pairs to said second controlled terminal of the second field effect transistor in said respective pair providing four output ports; f. conductor means for selectively electrically connecting said first controlled terminal of said second field effect transistor of each pair in a pattern such that the first controlled terminal of each second transistor is electrically connected directly to the same input lead as the gate of the corresponding first transistor of that pair; and g. conductor means for electrically connecting the gate of each second transistor of each pair directly to the input lead corresponding to the complement of the binary information signal associated with the input connected to the first controlled terminal of that second transistor.

Claim 6

In combination, a. means responsive to a first binary information signal for providing said first binary information signal on a first input lead and an inversion of said first binary information signal on a second input lead so as to provide first complementary binary information signals on the first and second leads; b. means responsive to a second binary information signal for providing said second binary information signal on a third input lead and an inversion of said second binary information signal on a fourth input lead so as to provide second complementary binary information signals on the third and fourth leads; c. four pairs of field effect transistors, each field effect transistor having a gate and first and second controlled terminals; d. conductor means for electrically connecting a selected one of the four input leads directly to the gate of a first transistor from each pair, and for electrically connecting a selected one of the two leads associated with the other binary information signal directly to the first controlled terminal of each first transistor, the conductor means being arranged so that the four first transistors are connected in a patteRn wherein each first transistor has its gate and its first controlled terminal connected to a different combination of two of the input leads (other than the leads corresponding to each binary information signal and its inversion); e. conductor means for electrically connecting said second controlled terminal of each of said first field effect transistors in each of said pairs to said second controlled terminal of the second field effect transistor in said respective pair providing four output ports; f. conductor means for selectively electrically connecting said first controlled terminal of said second field effect transistor of each pair in a pattern such that the first controlled terminal of each second transistor is electrically connected directly to the same input lead as the gate of the corresponding first transistor of that pair; and g. conductor means for electrically connecting the gate of each second transistor of each pair directly to the input lead corresponding to the complement of the binary information signal associated with the input connected to the first controlled terminal of that second transistor.

Claim 7

The combination as defined in claim 4 also including: four capacitors, each being electrically connected directly to a different corresponding one of said four output ports.

Claim 8

In combination, a. first, second, third, and fourth field effect transistors, each field effect transistor having a gate and first and second controlled terminals; b. means for electrically connecting said first controlled terminal of said first and second field effect transistors directly to each other to form a first input port; c. means for electrically connecting said second controlled terminal of said first and third field effect transistors directly to each other to form a first output port; d. means for electrically connecting said second controlled terminal of said second and fourth field effect transistors directly to each other to form a second output port; e. means for electrically connecting said gates of said first and fourth field effect transistors and said first controlled terminal of said third field effect transistor directly to each other to form a second input port; and f. means for electrically connecting said gates of said second and third field effect transistors and said first controlled terminal of said fourth field effect transistor directly to each other to form a third input port.

Claim 9

In combination, a. first, second, third, and fourth field effect transistors, each field effect transistor having a gate and first and second controlled terminals; b. means for electrically connecting said first controlled terminal of said first and second field effect transistors directly to each other to form a first input port; c. means for electrically connecting said second controlled terminal of said first and third field effect transistors directly to each other to form a first output port; d. means for electrically connecting said second controlled terminal of said second and fourth field effect transistors directly to each other to form a second output port; e. means for electrically connecting said gates of said first and fourth field effect transistors and said first controlled terminal of said third field effect transistor directly to each other to form a second input port; and f. means for electrically connecting said gates of said second and third field effect transistors and said first controlled terminal of said fourth field effect transistor directly to each other to form a third input port.

Claim 10

A binary decoding circuit comprising first and second circuits as recited in claim 6, for converting two-bit binary coded data signals A B into one-out-of-four logic signals, each bit A and B being such that one state is a voltage capable of turning any of the FETs ON and the other state is ground, the decoding circuit further comprising: g. first and second phase splitting circuits, each having an input and two outputs, for generating the first bit A and its complement A and the second bit B and its complement B; h. means for electrically connecting the phase-splitter output A to the first input port of the first claim 8 circuit, and for electrically connecting the output A to the first input port of the second claim 8 circuit; and i. means for electrically connecting the phase-splitter output B to the second input port of both claim 8 circuits, and for electrically connecting the output B to the third input port of both claim 8 circuits, whereby a voltage from A at the first output port of the first claim 8 circuit indicates the combination AB, a voltage from A at the second output port of the first claim circuit indicates AB, a voltage from A at the first output port of the second claim 8 circuit indicates AB, and a voltage at the second output port of the second claim 8 circuit indicates AB, and whereby all but the selected output port are connected to the ground of an associated one of the data bits and complements through associated ones of the transistoRs.

Claim 11

A decoding circuit as recited in claim 7, wherein: each output port is electrically connected to an output capacitor, corresponding one to each possible combination of the data signals, the capacitor selected for each combination being charged from the associated data input A or A through one of the first transistors, the other three capacitors being connected to ground of other data inputs through selected ones of the first, second, third and fourth transistors.

Claim 12

A logic circuit, comprising: a. an input conductor; b. a first gating device having an enabling gate electrode that permits the device to conduct current from a first terminal to a second terminal of the device, said gate electrode being electrically connected to be enabled by a predetermined gate voltage on a first conductor to connect said input conductor with a first output terminal; c. a first output capacitor electrically connected to the first output terminal; d. a second gating device having its gate electrode connected to be enabled by said predetermined gate voltage on a second conductor to connect said input conductor with a second output terminal; e. a second output capacitor electrically connected to the second output terminal; f. a third gating device having its gate electrode connected to be enabled by said predetermined gate voltage on the second conductor to complete a discharge path from the first output capacitor to ground; and g. a fourth gating device having its gate electrode connected to be enabled by said predetermined gate voltage on the first conductor to complete a discharge path from the second output capacitor to ground; h. the first and second conductors being energizable alternatively to said predetermined gate voltage, so that only one of the output capacitors will receive current from the input conductor to charge that capacitor depending on which of the first and second conductors is energized and so that the other output capacitor is discharged to ground if previously charged.

Claim 13

A logic circuit, comprising: a. an input conductor; b. a first gating device having an enabling gate electrode that permits the device to conduct current from a first terminal to a second terminal of the device, said gate electrode being electrically connected to be enabled by a predetermined gate voltage on a first conductor to connect said input conductor with a first output terminal; c. a first output capacitor electrically connected to the first output terminal; d. a second gating device having its gate electrode connected to be enabled by said predetermined gate voltage on a second conductor to connect said input conductor with a second output terminal; e. a second output capacitor electrically connected to the second output terminal; f. a third gating device having its gate electrode connected to be enabled by said predetermined gate voltage on the second conductor to complete a discharge path from the first output capacitor to ground; and g. a fourth gating device having its gate electrode connected to be enabled by said predetermined gate voltage on the first conductor to complete a discharge path from the second output capacitor to ground; h. the first and second conductors being energizable alternatively to said predetermined gate voltage, so that only one of the output capacitors will receive current from the input conductor to charge that capacitor depending on which of the first and second conductors is energized and so that the other output capacitor is discharged to ground if previously charged.