Circuit arrangement of mos transistors operating according to the dynamic principle for decoding the addresses for an mos memory

Claim 1

A decoder arrangement operating according to the dynamic principle for decoding addresses for an MOS transistor memory carried on a chip with the decoder arrangement, comprising: a plurality of partial decoder circuits each including a plurality of first MOS transistors, each of said transistors including a gate and a controlled conduction path having a first terminal connected to the like terminals of the other first transistors and forming a control line for a respective row of the memory and a second terminal connected to the like terminals of the other first transistors and exhibiting the distributed line capacitance with respect to a reference, and a second charging MOS transistor including a gate and a controlled conduction path having a first terminal connected to an operational potential and a second terminal connected to said first terminals of said plurality of first transistors, said gate of said second MOS transistor receiving clock pulses, a delay circuit including an input for receiving clock pulses and an output, said delay circuit operable to delay the trailing edge of a clock pulse, said output connected to said second terminals of said first transistors, said gates of said first transistors receiving respective binary address signals during a clock pulse, and a plurality of address signal inverters operable to invert the binary address signals after the trailing edge of a clock pulse and before the delayed trailing edge, whereby the combination of address and inverted address signals prevents the discharge of one of the distributed capacitances and effects discharge of the distributed capacitance of each other memory control line by way of the corresponding first transistors.