US4495222A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Metallization means and method for high temperature applications
Assignee: Motorola Solutions Inc
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Filing: 1983-11-07
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Granted: 1985-01-22
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Expires: 2003-11-07
Abstract
Abstract Semiconductor devices with resistor regions, capable of operating at higher temperatures, and having improved bond pull strength are obtained by using a single layer (e.g. Ni-Cr) to act as a combined resistive layer and barrier layer. When placed in the contact windows between the semiconductor (e.g. Si) and the interconnect metallization, (e.g. Al) and Ni-Cr layer acts as a diffusion barrier to prevent interdiffusion of silicon and aluminum and contact alloying punch-through. When placed elsewhere on the device the Ni-Cr layer also serves as thin film resistor material. Wire bond pull strength is improved by placing an adhesion layer (e.g. polysilicon) beneath the portion of the resistive barrier layer underlying the bonding pads. The polysilicon layer rests on the insulator (e.g. SiO2) covering the semiconductor substrate.
Inventors
- 👤 George F. Anderson
- 👤 Dan L. Burt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:13
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/101; H10D84/121; H10D84/125; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; H10W72/00; H10W72/01; H10W72/019; H10W70/00; H10W70/60; H10W72/50; H10W72/531; H10W72/536; H10W72/59; H10W72/90; H10W72/931; H10W72/934; H10W72/951; H10W72/952
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
66 words
In a process for forming bonding pads suitable for attachment of external bonding means, on an electrical device having a resistive barrier layer beneath said pads and on a substrate, the improvement comprising inserting between said substrate and said resistive barrier layer an adhesion layer comprising a material which forms intermetallic compounds with said resistive barrier layer and comprises an element in common with said substrate.
Claim 2
Dependent Claim
66 words
In a process for forming bonding pads suitable for attachment of external bonding means, on an electrical device having a resistive barrier layer beneath said pads and on a substrate, the improvement comprising inserting between said substrate and said resistive barrier layer an adhesion layer comprising a material which forms intermetallic compounds with said resistive barrier layer and comprises an element in common with said substrate.
Claim 3
Dependent Claim
30 words
The process of claim 1 wherein said substrate comprises a semiconductor at least partly covered by an insulating layer, and wherein said element is in common with said insulating layer.
Claim 4
Dependent Claim
32 words
The process of claim 2 wherein said semiconductor is silicon, said insulator comprises silicon dioxide or silicon nitride, said adhesion layer comprises poly-silicon, and said resistive barrier layer comprises nickel and chromium.
Claim 5
Dependent Claim
228 words
A process for making on the same electronic device a high strength bonding pad region and a resistor region, comprising: providing a substrate for supporting said bonding pad and said resistor region; covering a portion of said substrate with an insulator; forming an adhesion layer on a first portion of said insulator corresponding to the desired location of said bonding pad; forming a resistive barrier layer at least on said adhesion layer and said insulator; forming a bonding layer on said resistive barrier layer; patterning said bonding layer to leave said bonding layer at least on said bonding pad region and expose said underlying resistive barrier layer at least in said resistor region; patterning said resistive barrier layer to leave said resistive barrier layer at least in said resistor region and under said patterned bonding layer; prior to said first forming step, choosing a material for said adhesion layer adapted to form intermetallic compounds with the material of said resistive barrier layer and which has a constituent in common with the material of said insulator; and prior to said second forming step, choosing a material for said resistive barrier layer which has a resistivity not less than approximately 1×10 -4 ohm-cm and which is substantially impervious to the interdiffusion of the material of said substrate and the material of said bonding layer at temperatures below about 500° C.
Claim 6
Dependent Claim
228 words
A process for making on the same electronic device a high strength bonding pad region and a resistor region, comprising: providing a substrate for supporting said bonding pad and said resistor region; covering a portion of said substrate with an insulator; forming an adhesion layer on a first portion of said insulator corresponding to the desired location of said bonding pad; forming a resistive barrier layer at least on said adhesion layer and said insulator; forming a bonding layer on said resistive barrier layer; patterning said bonding layer to leave said bonding layer at least on said bonding pad region and expose said underlying resistive barrier layer at least in said resistor region; patterning said resistive barrier layer to leave said resistive barrier layer at least in said resistor region and under said patterned bonding layer; prior to said first forming step, choosing a material for said adhesion layer adapted to form intermetallic compounds with the material of said resistive barrier layer and which has a constituent in common with the material of said insulator; and prior to said second forming step, choosing a material for said resistive barrier layer which has a resistivity not less than approximately 1×10 -4 ohm-cm and which is substantially impervious to the interdiffusion of the material of said substrate and the material of said bonding layer at temperatures below about 500° C.
Claim 7
Dependent Claim
42 words
The process of claim 4 wherein said substrate comprises silicon, said insulator comprises silicon oxide or nitride or both, said adhesion layer comprise poly-silicon, and said resistive barrier layer comprises nickel and chromium, and wherein said bonding layer comprises aluminum or gold.
References Cited (Backward Citations)
US3256587A
Cited
US3585461A
Cited
US3617818A
Cited
US3942187A
Cited
US3689332A
Cited
US3761309A
Cited
US3840398A
Cited
US3830657A
Cited
US3935635A
Cited
US4005455A
Cited
US4050965A
Cited
US4162506A
Cited
US4087314A
Cited
US4151545A
Cited
US4188636A
Cited
US4206472A
Cited
US4201999A
Cited
US4222165A
Cited
US4184933A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-22 | 1988-07-23 | 1989-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-22 | 1992-07-23 | 1993-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-22 | 1996-07-23 | 1997-01-22 | $7700.00 | Window Closed / Lapsed |