High reliability semiconductive devices and integrated circuits
Abstract
Abstract A metallization process and structure for semiconductive devices and integrated circuits with a high degree of protection against impurities affecting device characteristics is provided having a first insulating layer, such as one of thermally grown silicon dioxide, formed on the device with openings where contacts are desired, a first metal layer forming contacts and interconnections between selected contacts of a metal such as aluminum, a second dielectric layer such as a glass layer with openings only over those portions of the previous metal layer in bonding pad areas, a second metal layer of a material, such as titanium, very tightly adherent to the glass dielectric deposited within and around the opening of the second insulating layer covered by a third metal layer preferably of gold with a gold lead wire bonded thereto or other means for external connection.
Inventors
- 👤 Robert T Eynon
- 👤 Richard Criswell Grace
Bibliographic Details
Claims Analysis
Total Claims: 0References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-14 | 1974-12-14 | 1975-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-14 | 1978-12-14 | 1979-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-14 | 1982-12-14 | 1983-06-15 | $7700.00 | Window Closed / Lapsed |