Bonding pedestals for semiconductor devices

Claim 1

A process for the formation of a bonding pedestal for a multileaded semiconductor device having aluminum or an aluminum alloy on-chip metallization covered with a passivating glass with vias exposing portions of said metallization therethrough, comprising: sputtering depositing a thin layer consisting of a mixture of Ti--W over the on-chip metallization; sputtering depositing a thin layer of a third metal suitable as a plating base over said Ti--W layer; selectively plating a thick layer of a metal selected from the group consisting of Ni, Cu, Ag, and Au over portions of said third metal over said vias but said thick layer not subtending all of said on-chip metallization; removing said third metal in areas where the thick layer was not plated; and etching said Ti--W layer in areas where the thick layer was not plated in an etchant which has an extremely slow attack rate of said on-chip metallization.