Message identification and data entry apparatus

Claim 1

Apparatus for the recognition and decoding of digital and analog information by comparing received data with a stored data word and comparing bits of the received data with each other in a predetermined order, comprising: first comparator circuit means for comparing received data with a stored data word and providing a message identification and acceptance output signal in response to a correlation between said received data and said stored data word, second comparator circuit means for comparing bits of said received data with each other in a predetermined order and producing decoded output data in response to a correlation of the compared bits, error detection circuit means coupled to the output of said first and second comparator circuit means and providing an output error signal when there is no data decoded from said second comparator circuit, and data complement check clock generating means being connected to and being controlled by the output of said first comparator circuit means and having an output connected to said error detection circuit means for providing precise time synchronization between the outputs of said first and second comparator circuit means.