US4007439A
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Select high/low register method and apparatus
Assignee: Unisys Corp
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Filing: 1975-08-18
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Granted: 1977-02-08
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Expires: 1995-08-18
Abstract
Abstract In a large parallel processing environment including a plurality of active registers storing either normalized floating point or integer data a high/low register selection circuit identifies selectively the register or registers storing either the highest or lowest numerical data value. The numerical data in each active register is first converted into a pure binary magnitude pattern having the same relative value as the original numerical data for a select high register search, and the inverse relative value for a select low register search. Thereafter, the binary patterns from all active registers are processed together two bits at a time through an OR network with the OR network output functioning to deactivate all registers having an OR'ed two bit pattern less than the OR network output value. The deactivating process is continued two bits at a time until either only one register remains active or all bits have been processed two bits at a time through the OR network.
Inventors
- 👤 Carl Frederick Semmelhaack
- 👤 Mark Camillo Divecchio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:08
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/22
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
305 words
An apparatus for selecting certain logic elements in a plurality of logic elements, said apparatus including: a plurality of logic elements; means for activating individual logic elements in said plurality of logic elements; a first register in each logic element of said plurality of logic elements, each said first register for storing a numerical value; converter means associated with each said first register and inputted therefrom, each said converter means for converting said numerical value stored in said first register associated therewith into a pure binary number; a second register associated with each said converter means inputted therefrom, each said second register for storing said pure binary number of said converter means associated therewith; means controlling each said second register for repetitively shifting out therefrom at least 2 bits at a time said pure binary stored therein sequentially from the most significant bit to the least significant bit; means responding to each shifting by said repetitively shifting means for comparing said at least 2 bits shifted out of said second register of each active logic element in said plurality of logic elements with all other said at least 2 bits so shifted out of all other active logic elements in said plurality of logic elements, and for deactivating all active logic elements in said plurality of logic elements having said at least 2 bits shifted out thereof of lower value than said at least two bits shifted out of any other active logic element in said plurality of logic elements; and means monitoring said repetitively shifting means for indicating when all bits of said pure binary number have been shifted out of each said second register and compared by said means for comparing and deactivating whereby all logic elements in said plurality of logic elements remaining active after said indicating are indicated as being selected.
Claim 2
Independent Claim
305 words
An apparatus for selecting certain logic elements in a plurality of logic elements, said apparatus including: a plurality of logic elements; means for activating individual logic elements in said plurality of logic elements; a first register in each logic element of said plurality of logic elements, each said first register for storing a numerical value; converter means associated with each said first register and inputted therefrom, each said converter means for converting said numerical value stored in said first register associated therewith into a pure binary number; a second register associated with each said converter means inputted therefrom, each said second register for storing said pure binary number of said converter means associated therewith; means controlling each said second register for repetitively shifting out therefrom at least 2 bits at a time said pure binary stored therein sequentially from the most significant bit to the least significant bit; means responding to each shifting by said repetitively shifting means for comparing said at least 2 bits shifted out of said second register of each active logic element in said plurality of logic elements with all other said at least 2 bits so shifted out of all other active logic elements in said plurality of logic elements, and for deactivating all active logic elements in said plurality of logic elements having said at least 2 bits shifted out thereof of lower value than said at least two bits shifted out of any other active logic element in said plurality of logic elements; and means monitoring said repetitively shifting means for indicating when all bits of said pure binary number have been shifted out of each said second register and compared by said means for comparing and deactivating whereby all logic elements in said plurality of logic elements remaining active after said indicating are indicated as being selected.
Claim 3
Dependent Claim
189 words
The apparatus according to claim 1 wherein each said numerical value stored in each said first register comprises an exponent sign bit, a digital exponent field, an integer/fraction sign bit, and a digital integer/fraction field, and wherein each said converter means includes: controller means having a first and a second logical state for controlling conversion of said numerical digital value stored; means for complementing said exponent sign bit when both said integer/fraction sign bit equals a logical zero and said controller means is in said first logical state and when both said integer/fraction sign bit equals a logical one and said controller means is in said second logical state; means for complementing said exponent field when both said integer/fraction sign bit equals a logical 1 and said controller means is in said first logical state and when both said integer/fraction sign bit equals a logical 0 and said controller means is in said second logical state; means for complementing said integer/fraction field when said controller means is in said second logical state; and means for complementing said integer/fraction bit when said controller means is in said first logical state.
Claim 4
Dependent Claim
77 words
The apparatus according to claim 1 wherein said pure binary number stored in said second register of each logic element in said plurality of logic elements is of the same relative order with respect to each said pure binary number stored in each other said second register as said numerical value stored in said first register of the same logic element is with respect to each other said numerical value stored in each other said first register.
Claim 5
Dependent Claim
79 words
The apparatus according to claim 3 wherein said numerical value stored in each said first register comprises an exponent sign bit, a digital exponent field, an integer/fraction sign bit, and a digital integer/fraction field, and wherein each said converter means includes: means for complementing said exponent sign bit when said integer/fraction sign bit equals a logical ; means for complementing said exponent field when said integer/fraction sign bit equals a logical 1; and means for complementing said integer/fractions bit.
Claim 6
Dependent Claim
78 words
The apparatus according to claim 1 wherein said pure binary number stored in said second register of each logic element in said plurality of logic elements is of the inverse relative order with respect to each other said pure binary number stored in each other said second register as said numerical value stored in said first register of the same logic element is with respect to each other said numerical value stored in each other said first register.
Claim 7
Dependent Claim
79 words
The apparatus according to claim 5 wherein said numerical value stored in each said first register comprises an exponent sign bit, a digital exponent field, an integer/fraction sign bit, and a digital integer/fraction field; and wherein each said converter means includes: means for complementing said exponent sign bit when said integer/fraction sign bit equals a logical one; means for complementing said exponent field when said integer/fraction sign bit equals a logical zero; and means for complementing said integer/fraction field.
Claim 8
Independent Claim
161 words
A method of selecting certain logic elements in a plurality of logic elements, said method comprising the steps of: activating individual logic elements in the plurality of logic elements; storing in each said activated logic element a numerical value associated therewith; converting in each said activated logic element said associated numerical value stored therein into a pure binary number; storing in each said activated logic element said pure binary number converted therein; repetitively comparing all said stored pure binary numbers at least two bits at a time from the most significant bits to the least significant bits; and deactivating in response to said step of comparing each said activated logic element in the plurality of logic elements having said pure binary number stored therein of lower value than said pure binary number stored in any other said activated element whereby all logic elements in the plurality of logic elements remaining active after said step of deactivating are indicated as being selected.
Claim 9
Independent Claim
161 words
A method of selecting certain logic elements in a plurality of logic elements, said method comprising the steps of: activating individual logic elements in the plurality of logic elements; storing in each said activated logic element a numerical value associated therewith; converting in each said activated logic element said associated numerical value stored therein into a pure binary number; storing in each said activated logic element said pure binary number converted therein; repetitively comparing all said stored pure binary numbers at least two bits at a time from the most significant bits to the least significant bits; and deactivating in response to said step of comparing each said activated logic element in the plurality of logic elements having said pure binary number stored therein of lower value than said pure binary number stored in any other said activated element whereby all logic elements in the plurality of logic elements remaining active after said step of deactivating are indicated as being selected.
Claim 10
Independent Claim
168 words
An apparatus for selecting certain logic elements in a plurality of logic elements comprising: means for activating individual logic elements in the plurality of logic elements; means for storing in each said activated logic element a numerical value associated therewith; means for converting in each said activated logic element said associated numerical value stored therein into a pure binary number; means for storing in each said activated logic element said pure binary number converted therein; means for repetitively comparing all said stored pure binary numbers at least 2 bits at a time from the most significant bits to the least significant bits; and means for deactivating in response to said step of comparing each said activated logic element in the plurality of logic elements having said pure binary number stored therein of lower value than said pure binary number stored in any other said activated element whereby all logic elements in the plurality of logic elements remaining active after said step of deactivating are indicated as being selected.
Claim 11
Independent Claim
168 words
An apparatus for selecting certain logic elements in a plurality of logic elements comprising: means for activating individual logic elements in the plurality of logic elements; means for storing in each said activated logic element a numerical value associated therewith; means for converting in each said activated logic element said associated numerical value stored therein into a pure binary number; means for storing in each said activated logic element said pure binary number converted therein; means for repetitively comparing all said stored pure binary numbers at least 2 bits at a time from the most significant bits to the least significant bits; and means for deactivating in response to said step of comparing each said activated logic element in the plurality of logic elements having said pure binary number stored therein of lower value than said pure binary number stored in any other said activated element whereby all logic elements in the plurality of logic elements remaining active after said step of deactivating are indicated as being selected.
Claim 12
Dependent Claim
31 words
The apparatus according to claim 8 wherein said means for storing a numerical value includes a first register and said means for storing said pure binary number includes a second register.
Claim 13
Dependent Claim
70 words
The apparatus according to claim 8 wherein said numerical value comprises an exponent sign bit, an exponent field, an integer/fraction sign bit, and an integer/fraction field, and wherein said means for converting includes means for complementing said exponent sign bit when said integer/fraction sign bit equals a logical 0; means for complementing said exponent field when integer/fraction sign bit equals to logical 1; and means for complementing said integer/fraction bit.
Claim 14
Dependent Claim
72 words
The apparatus according to claim 8 wherein said numerical value comprises an exponent sign bit, an exponent field, an integer/fraction sign bit, and an integer/fraction field; and wherein each said means for converting includes: means for complementing said exponent sign bit when said integer/fraction sign bit equals a logical 1; means for complementing said exponent field when said integer/fraction sign bit equals a logical 0; and means for complementing said integer/fraction field.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-02-08 | 1980-08-09 | 1981-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-02-08 | 1984-08-09 | 1985-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-02-08 | 1988-08-09 | 1989-02-08 | $7700.00 | Window Closed / Lapsed |