US3713095A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processor sequence checking circuitry
Assignee: AT&T Inc
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Filing: 1971-03-16
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Granted: 1973-01-23
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Expires: 1991-03-16
Abstract
Abstract Apparatus for detecting illogical sequences of operations in digital processor units. Apparatus comprising logic gates is included at several points within a processor unit to provide early detection of hardware failures. The apparatus is designed to monitor the sequence of operations that occur when particular processor registers are loaded from a plurality of sources and unloaded to a plurality of destinations.
Inventors
- 👤 A Mcpherson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 04:54
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/28; G06F5/00; G06F5/06; G06F5/10
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
146 words
An error detection circuit for a digital storage device having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising; means connected to said load control means for detecting undesired simultaneous commands to load said data storage device from more than one of said plurality of inputs; means connected to said unload control means for detecting undesired simultaneous commands to unload said data storage device to more than one of said plurality of outputs; means connected to both said load control means and said unload control means for detecting an improper sequence of commands to load and unload said data storage device; and means responsive to each of said detecting means for generating an error signal.
Claim 2
Dependent Claim
146 words
An error detection circuit for a digital storage device having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising; means connected to said load control means for detecting undesired simultaneous commands to load said data storage device from more than one of said plurality of inputs; means connected to said unload control means for detecting undesired simultaneous commands to unload said data storage device to more than one of said plurality of outputs; means connected to both said load control means and said unload control means for detecting an improper sequence of commands to load and unload said data storage device; and means responsive to each of said detecting means for generating an error signal.
Claim 3
Dependent Claim
220 words
An error detection circuit for a digital storage device having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said load control means for detecting the condition of said data storage device not being loaded by any of said plurality of inputs when a load command is given by said load control means; means connected to said load control means for detecting undesired simultaneous commands to load said data storage device from more than one of said plurality of inputs; means connected to said unload control means for detecting the condition of said data storage device not being unloaded to any of said plurality of outputs when an unload command is given by said unload control means; means connected to said unload control means for detecting undesired simultaneous commands to unload said data storage device to more than one of said plurality of outputs; means connected to both said load control means and said unload control means for detecting an improper sequence of commands to load and unload said data storage device; and means responsive to each of said detecting means for generating an error signal.
Claim 4
Dependent Claim
220 words
An error detection circuit for a digital storage device having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said load control means for detecting the condition of said data storage device not being loaded by any of said plurality of inputs when a load command is given by said load control means; means connected to said load control means for detecting undesired simultaneous commands to load said data storage device from more than one of said plurality of inputs; means connected to said unload control means for detecting the condition of said data storage device not being unloaded to any of said plurality of outputs when an unload command is given by said unload control means; means connected to said unload control means for detecting undesired simultaneous commands to unload said data storage device to more than one of said plurality of outputs; means connected to both said load control means and said unload control means for detecting an improper sequence of commands to load and unload said data storage device; and means responsive to each of said detecting means for generating an error signal.
Claim 5
Dependent Claim
150 words
An error detection circuit for a register having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and being unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said load control means for detecting undesired simultaneous commands to load said register from more than one of said plurality of inputs; means connected to said unload control means for detecting undesired simultaneous commands to unload said register to more than one of said plurality of outputs; means connected to both said load control means and said unload control means for detecting the conditions of said register being loaded twice in succession without being unloaded or being unloaded twice in succession without being loaded; and means responsive to each of said detecting means for generating an error signal.
Claim 6
Dependent Claim
150 words
An error detection circuit for a register having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and being unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said load control means for detecting undesired simultaneous commands to load said register from more than one of said plurality of inputs; means connected to said unload control means for detecting undesired simultaneous commands to unload said register to more than one of said plurality of outputs; means connected to both said load control means and said unload control means for detecting the conditions of said register being loaded twice in succession without being unloaded or being unloaded twice in succession without being loaded; and means responsive to each of said detecting means for generating an error signal.
Claim 7
Dependent Claim
75 words
The error detection circuit of claim 3 wherein said means for detecting undesired simultaneous commands to load said register further comprises: a plurality of AND gates connected to the control lines of said load control means that are used to load said register, said AND gates being connected so as to AND together all possible two-at-a-time combinations of said control lines; and an OR gate connected to the outputs of said plurality of AND gates.
Claim 8
Dependent Claim
75 words
The error detection circuit of claim 3 wherein said means for detecting undesired simultaneous commands to unload said register further comprises: a Plurality of AND gates connected to the control lines of said unload control means that are used to unload said register, said AND gates being connected so as to AND together all possible two-at-a-time combinations of said control lines; and an OR gate connected to the outputs of said plurality of AND gates.
Claim 9
Dependent Claim
66 words
The error detection circuit of claim 3 wherein said means for detecting the conditions of said register being loaded twice in succession without being unloaded or being unloaded twice in succession without being loaded further comprises: a one-bit memory connected both to said means for detecting undesired simultaneous commands to load said register and to said means for detecting undesired simultaneous commands to unload said register.
Claim 10
Dependent Claim
20 words
The error detection circuit of claim 3 wherein said means for generating an error signal further comprises: an OR gate.
Claim 11
Dependent Claim
220 words
An error detection circuit for a register having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and being unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said load control means for detecting the condition of said register not being loaded by any of said plurality of inputs when a load command is given by said load control means; means connected to said load control means for detecting undesired simultaneous commands to load said register from more than one of said plurality of inputs; means connected to said unload control means for detecting the condition of said register not being unloaded to any of said plurality of outputs when an unload command is given by said unload control means; means connected to said unload control means for detecting undesired simultaneous commands to unload said register to more than one of said plurality of outputs; means connected to both said load control means and said unload control means for detecting the conditions of said register being loaded twice in succession without being unloaded or being unloaded twice in succession without being loaded; and means responsive to each of said detecting means for generating an error signal.
Claim 12
Dependent Claim
220 words
An error detection circuit for a register having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and being unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said load control means for detecting the condition of said register not being loaded by any of said plurality of inputs when a load command is given by said load control means; means connected to said load control means for detecting undesired simultaneous commands to load said register from more than one of said plurality of inputs; means connected to said unload control means for detecting the condition of said register not being unloaded to any of said plurality of outputs when an unload command is given by said unload control means; means connected to said unload control means for detecting undesired simultaneous commands to unload said register to more than one of said plurality of outputs; means connected to both said load control means and said unload control means for detecting the conditions of said register being loaded twice in succession without being unloaded or being unloaded twice in succession without being loaded; and means responsive to each of said detecting means for generating an error signal.
Claim 13
Dependent Claim
135 words
An error detection circuit for a register having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and being unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said load control means for detecting the condition of said register not being loaded from any of said plurality of inputs when a load command is given by said load control means; means connected to both said load control means and said unload control means for detecting the conditions of said register being loaded twice in succession without being unloaded or being unloaded twice in succession without being loaded; and means responsive to each of said detecting means for generating an error signal.
Claim 14
Dependent Claim
135 words
An error detection circuit for a register having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and being unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said load control means for detecting the condition of said register not being loaded from any of said plurality of inputs when a load command is given by said load control means; means connected to both said load control means and said unload control means for detecting the conditions of said register being loaded twice in succession without being unloaded or being unloaded twice in succession without being loaded; and means responsive to each of said detecting means for generating an error signal.
Claim 15
Dependent Claim
135 words
An error detection circuit for a register having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and being unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said unload control means for detecting the condition of said register not being unloaded to any of said plurality of outputs when an unload command is given by said unload control means; means connected to both said load control means and said unload control means for detecting the conditions of said register being loaded twice in succession without being unloaded or being unloaded twice in succession without being loaded; and means responsive to each of said detecting means for generating an error signal.
Claim 16
Dependent Claim
135 words
An error detection circuit for a register having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and being unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said unload control means for detecting the condition of said register not being unloaded to any of said plurality of outputs when an unload command is given by said unload control means; means connected to both said load control means and said unload control means for detecting the conditions of said register being loaded twice in succession without being unloaded or being unloaded twice in succession without being loaded; and means responsive to each of said detecting means for generating an error signal.
Claim 17
Dependent Claim
105 words
An error detection circuit for a register having the capabilitY of being loaded by a plurality of inputs in response to commands generated by a load control means, said circuit comprising: means connected to said load control means for detecting the condition of said register not being loaded by any of said plurality of inputs when a load command is given by said load control means; means connected to said load control means for detecting undesired simultaneous commands to load said register from more than one of said plurality of inputs; and means responsive to each of said detecting means for generating an error signal.
Claim 18
Dependent Claim
105 words
An error detection circuit for a register having the capabilitY of being loaded by a plurality of inputs in response to commands generated by a load control means, said circuit comprising: means connected to said load control means for detecting the condition of said register not being loaded by any of said plurality of inputs when a load command is given by said load control means; means connected to said load control means for detecting undesired simultaneous commands to load said register from more than one of said plurality of inputs; and means responsive to each of said detecting means for generating an error signal.
Claim 19
Dependent Claim
105 words
An error detection circuit for a register having the capability of being unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said unload control means for detecting the condition of said register not being unloaded to any of said plurality of outputs when an unload command is given by said unload control means; means connected to said unload control means for detecting undesired simultaneous commands to unload said register to more than one of said plurality of outputs; and means responsive to each of said detecting means for generating an error signal.
Claim 20
Dependent Claim
105 words
An error detection circuit for a register having the capability of being unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said unload control means for detecting the condition of said register not being unloaded to any of said plurality of outputs when an unload command is given by said unload control means; means connected to said unload control means for detecting undesired simultaneous commands to unload said register to more than one of said plurality of outputs; and means responsive to each of said detecting means for generating an error signal.
Claim 21
Dependent Claim
133 words
An error detection circuit for a register having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and being unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said load control means for detecting the condition of said register not being loaded by any of said plurality of inputs when a load command is given by said load control means; means connected to said unload control means for detecting the condition of said register not being unloaded to any of said plurality of outputs when an unload command is given by said unload control means; and means responsive to each of said detecting means for generating an error signal.
Claim 22
Dependent Claim
133 words
An error detection circuit for a register having the capability of being loaded by a plurality of inputs in response to commands generated by a load control means and being unloaded to a plurality of outputs in response to commands generated by an unload control means, said circuit comprising: means connected to said load control means for detecting the condition of said register not being loaded by any of said plurality of inputs when a load command is given by said load control means; means connected to said unload control means for detecting the condition of said register not being unloaded to any of said plurality of outputs when an unload command is given by said unload control means; and means responsive to each of said detecting means for generating an error signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-23 | 1976-07-24 | 1977-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-23 | 1980-07-24 | 1981-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-23 | 1984-07-24 | 1985-01-23 | $7700.00 | Window Closed / Lapsed |