US4200838A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for evaluating the error rate of binary digital signals
Assignee: Individual
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Filing: 1978-04-28
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Granted: 1980-04-29
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Expires: 1998-04-28
Abstract
Abstract Apparatus for evaluating the error rate of a binary digital signal transmitted according to a multiple level modulation process in which a received signal is connected to a main and an auxiliary demodulator in parallel, the auxiliary modulator including means to disturb the signal, the output from the main demodulator being applied to a comparator to provide a first signal according to the comparison of a first signal pattern with a second signal pattern and the auxiliary demodulator including a comparator whose output provides a second signal according to the state of modulation of first and second received signals, the first and second signals being applied to a modulo 2 adder whose output is applied to a counter.
Inventors
- 👤 Jean-Pierre R. Poitevin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:19
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/24; H04L1/241
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
270 words
Apparatus for the evaluation of an error rate of bits transmitted over a digital link according to a multiple level modulation process, said apparatus including a main and regulated demodulator having an input and an auxiliary demodulator for detecting disturbances and having an input, the respective inputs of the main and auxiliary demodulators being connected in parallel to the receiving end of the digital link, said main demodulator normally providing an output signal responsive to signals received over said link, said auxiliary demodulator being operated to change said normal output responsive to error conditions, the apparatus further including first comparison circuit means for comparing m bits of each bit pattern with m bits of the preceding bit pattern and for giving a first binary signal if the two compared bit patterns from said output of the main demodulator are identical to each other and for giving a second binary signal if the two compared bit patterns are not identical to each other, and second comparison circuit means incorporated in the auxiliary demodulator for comparing the state of modulation of the received signal with the state of modulation of the preceding signal and for giving a first binary signal in the event of agreement and for giving a second binary signal in the event that said states of modulation are different from each other, modulo 2 adder means, the outputs of the first and second comparison circuit means being respectively connected to the inputs of the modulo 2 adder, and counter means, the output of the modulo 2 adder means being connected to the counter means to register the output thereof.
Claim 2
Dependent Claim
270 words
Apparatus for the evaluation of an error rate of bits transmitted over a digital link according to a multiple level modulation process, said apparatus including a main and regulated demodulator having an input and an auxiliary demodulator for detecting disturbances and having an input, the respective inputs of the main and auxiliary demodulators being connected in parallel to the receiving end of the digital link, said main demodulator normally providing an output signal responsive to signals received over said link, said auxiliary demodulator being operated to change said normal output responsive to error conditions, the apparatus further including first comparison circuit means for comparing m bits of each bit pattern with m bits of the preceding bit pattern and for giving a first binary signal if the two compared bit patterns from said output of the main demodulator are identical to each other and for giving a second binary signal if the two compared bit patterns are not identical to each other, and second comparison circuit means incorporated in the auxiliary demodulator for comparing the state of modulation of the received signal with the state of modulation of the preceding signal and for giving a first binary signal in the event of agreement and for giving a second binary signal in the event that said states of modulation are different from each other, modulo 2 adder means, the outputs of the first and second comparison circuit means being respectively connected to the inputs of the modulo 2 adder, and counter means, the output of the modulo 2 adder means being connected to the counter means to register the output thereof.
Claim 3
Dependent Claim
276 words
Apparatus for the evaluation of an error rate of bits transmitted over a digital link according to modulation coding of the transitional type, said apparatus including a main and regulated demodulator having an input and an auxiliary demodulator for detecting disturbances and having an input, the respective inputs of the main and auxiliary demodulators being connected in parallel to the receiving end of the digital link, said main demodulator normally providing an output signal responsive to signals received over said link, said auxiliary demodulator being operated to change said normal output responsive to error conditions, the apparatus further including first comparison circuit means for comparing m bits of each bit pattern with m bits of the predetermined bit pattern corresponding to the identical state modulation and for giving a first binary signal if the two compared bit patterns of said output of the main demodulator correspond to each other and for giving a second binary signal if the two compared bit patterns are not identical to each other, and second comparison circuit means incorporated in the auxiliary demodulator for comparing the state of modulation of the received signal with the state of modulation of the preceding signal and for giving a first binary signal in the event of agreement and for giving a second binary signal in the event that said states of modulation are different from each other, modulo 2 adder means, the outputs of the first and second comparison circuit means being respectively connected to the inputs of the modulo 2 adder, and counter means, the output of the modulo 2 adder means being connected to the counter means to register the output thereof.
Claim 4
Dependent Claim
276 words
Apparatus for the evaluation of an error rate of bits transmitted over a digital link according to modulation coding of the transitional type, said apparatus including a main and regulated demodulator having an input and an auxiliary demodulator for detecting disturbances and having an input, the respective inputs of the main and auxiliary demodulators being connected in parallel to the receiving end of the digital link, said main demodulator normally providing an output signal responsive to signals received over said link, said auxiliary demodulator being operated to change said normal output responsive to error conditions, the apparatus further including first comparison circuit means for comparing m bits of each bit pattern with m bits of the predetermined bit pattern corresponding to the identical state modulation and for giving a first binary signal if the two compared bit patterns of said output of the main demodulator correspond to each other and for giving a second binary signal if the two compared bit patterns are not identical to each other, and second comparison circuit means incorporated in the auxiliary demodulator for comparing the state of modulation of the received signal with the state of modulation of the preceding signal and for giving a first binary signal in the event of agreement and for giving a second binary signal in the event that said states of modulation are different from each other, modulo 2 adder means, the outputs of the first and second comparison circuit means being respectively connected to the inputs of the modulo 2 adder, and counter means, the output of the modulo 2 adder means being connected to the counter means to register the output thereof.
References Cited (Backward Citations)
US4064459A
Cited
US4091240A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-04-29 | 1983-10-29 | 1984-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-04-29 | 1987-10-29 | 1988-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-04-29 | 1991-10-29 | 1992-04-29 | $7700.00 | Window Closed / Lapsed |