US4473939A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for fabricating GaAs FET with ion implanted channel layer
Assignee: Raytheon Co
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Filing: 1982-12-27
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Granted: 1984-10-02
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Expires: 2002-12-27
Abstract
Abstract There is herein described a process for fabricating GaAs FETs with an ion implanted channel layer wherein an ion implanted substrate is capless annealed under an arsine overpressure, and a relatively shallow portion of the outer surface of the substrate in the active layer is removed for the deposition of a gate metallic electrode.
Inventors
- 👤 Milton Feng
- 👤 Victor K. Eu
- 👤 Hilda Kanber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:12
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/80; H10D30/87; H10D30/877; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125; H10P; H10P95/00; H10P95/90; H10P95/904; Y; Y10; Y10S; Y10S438/00; Y10S438/909
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
153 words
A process for fabricating a GaAs FET with ion implanted channel layer including the steps of: (a) providing a semi-insulating GaAs substrate; (b) implanting n-type ions through a surface of said substrate to produce an n-type active layer in said substrate; (c) capless annealing said substrate under AsH 3 overpressure in a non-reactive gas to a predetermined elevated temperature sufficient to remove substantial amounts of ion implantation damage in said substrate and to electrically activate said active layer, said overpressure being approximately 100 times that of the equilibrium As 4 pressure of said GaAs at said elevated temperature; (d) depositing source and drain ohmic contact metalizations on said surface of said substrate in spaced relationship; (e) removing a relatively shallow portion of the outer surface of said substrate in said active layer intermediate said source-and-drain contact metalizations for a gate electrical contact; and (f) depositing a gate metalization in said shallow removed portion.
Claim 2
Dependent Claim
153 words
A process for fabricating a GaAs FET with ion implanted channel layer including the steps of: (a) providing a semi-insulating GaAs substrate; (b) implanting n-type ions through a surface of said substrate to produce an n-type active layer in said substrate; (c) capless annealing said substrate under AsH 3 overpressure in a non-reactive gas to a predetermined elevated temperature sufficient to remove substantial amounts of ion implantation damage in said substrate and to electrically activate said active layer, said overpressure being approximately 100 times that of the equilibrium As 4 pressure of said GaAs at said elevated temperature; (d) depositing source and drain ohmic contact metalizations on said surface of said substrate in spaced relationship; (e) removing a relatively shallow portion of the outer surface of said substrate in said active layer intermediate said source-and-drain contact metalizations for a gate electrical contact; and (f) depositing a gate metalization in said shallow removed portion.
Claim 3
Dependent Claim
19 words
The process for fabricating a GaAs FET according to claim 1, wherein said non-reactive gas is H 2 .
Claim 4
Dependent Claim
17 words
The process for fabricating a GaAs FET according to claim 1, wherein said gate metalization is aluminum.
Claim 5
Dependent Claim
25 words
The process for fabricating a GaAs FET according to claim 1, wherein the depth of said relatively shallow portion is approximately 400 Å to 800/Å.
Claim 6
Dependent Claim
23 words
The process for fabricating a GaAs FET according to claim 1, wherein said predetermined temperature is between about 800° C. and 1000° C.
Claim 7
Dependent Claim
23 words
The process for fabricating a GaAs FET according to claim 1, wherein the partial pressure of said AsH 3 equals about 0.021 atm.
Claim 8
Dependent Claim
171 words
A process for fabricating a GaAs FET with ion implanted channel layer including the steps of: (a) providing a semi-insulating GaAs substrate; (b) providing an undoped high resistivity buffer layer over said substrate; (c) implanting n-type ions through a surface of said buffer layer to produce an n-type active layer in said buffer layer; (d) capless annealing said buffer layer and said substrate under AsH 3 overpressure in a non-reactive gas to a predetermined elevated temperature sufficient to remove substantial amounts of ion implantation damage in said buffer layer and to electrically activate said active layer, said overpressure being approximately 100 times that of the equilibrium As 4 pressure of said As at said elevated temperature; (e) depositing source-and-drain ohmic contact metalizations on said surface of said buffer layer in spaced relationship; (f) removing a relatively shallow portion of the outer surface of said buffer layer in said active layer intermediate said source-and-drain contact metalizations for a gate electrical contact; and (g) depositing a gate metalization in said shallow removed portion.
Claim 9
Dependent Claim
171 words
A process for fabricating a GaAs FET with ion implanted channel layer including the steps of: (a) providing a semi-insulating GaAs substrate; (b) providing an undoped high resistivity buffer layer over said substrate; (c) implanting n-type ions through a surface of said buffer layer to produce an n-type active layer in said buffer layer; (d) capless annealing said buffer layer and said substrate under AsH 3 overpressure in a non-reactive gas to a predetermined elevated temperature sufficient to remove substantial amounts of ion implantation damage in said buffer layer and to electrically activate said active layer, said overpressure being approximately 100 times that of the equilibrium As 4 pressure of said As at said elevated temperature; (e) depositing source-and-drain ohmic contact metalizations on said surface of said buffer layer in spaced relationship; (f) removing a relatively shallow portion of the outer surface of said buffer layer in said active layer intermediate said source-and-drain contact metalizations for a gate electrical contact; and (g) depositing a gate metalization in said shallow removed portion.
Claim 10
Dependent Claim
19 words
The process for fabricating a GaAs FET according to claim 7, wherein said non-reactive gas is H 2 .
Claim 11
Dependent Claim
17 words
The process for fabricating a GaAs FET according to claim 7, wherein said gate metalization is aluminum.
Claim 12
Dependent Claim
25 words
The process for fabricating a GaAs FET according to claim 7, wherein the depth of said relatively shallow portion is approximately 400 Å to 800/Å.
Claim 13
Dependent Claim
23 words
The process for fabricating a GaAs FET according to claim 7, wherein said predetermined temperature is between about 800° C. and 1000° C.
Claim 14
Dependent Claim
23 words
The process for fabricating a GaAs FET according to claim 7, wherein the partial pressure of said AsH 3 equals about 0.021 atm.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-02 | 1988-04-02 | 1988-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-02 | 1992-04-02 | 1992-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-02 | 1996-04-02 | 1996-10-02 | $7700.00 | Window Closed / Lapsed |