Patent US4437024A successfully refreshed from Google Patents.
US4437024A
Expired / Lapsed
US
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Actively controlled input buffer
Assignee: Intersil Corp
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Filing: 1981-10-22
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Granted: 1984-03-13
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Expires: 2001-10-22
Abstract
Abstract An interface circuit for producing output signals of first and second levels in response to input signals intermediate said first and second levels. The circuit includes a controllable impedance means, normally set to a high impedance condition, connected in series with a first insulated-gate field-effect transistor (IGFET) between a first power terminal and an output terminal and a second IGFET of complementary conductivity to said first IGFET connected between the output terminal and a second power terminal. In response to an input signal having a value to turn-on the second IGFET, the output terminal is driven to the voltage at the second power terminal and the first IGFET is set to an off condition, conducting at most the current flowing through the controllable impedance means set to its high impedance condition. In response to an input signal of a polarity and magnitude to turn-on the first IGFET and turn-off the second IGFET, a pulse generator coupled between the output terminal and the controllable impedance means momentarily places the controllable impedance means in a relatively low impedance condition and charges the output terminal to the voltage at the first power terminal.
Inventors
- 👤 Ihor T. Wacyk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:02
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
174 words
The combination comprising: first and second IGFETs of complementary conductivity type, each IGFET having source and drain electrodes defining the ends of a conduction path and a control electrode; a signal input terminal, a signal output terminal, and first and second power terminals for the application therebetween of an operating potential; means connecting the control electrodes of said first and second IGFETs to said signal input terminal; means connecting the drain electrodes of said first and second IGFETs to said signal output terminal; a controllable impedance means connected between said source of said first IGFET and said first power terminal, said controllable impedance means normally providing a relatively high impedance path when said first IGFET is turned on; means connecting said source of said second IGFET to said second power terminal; and pulse generating means coupled between said signal output terminal and said controllable impedance means for momentarily placing said controllable impedance means in a relatively low impedance condition in response to said first IGFET being driven from an OFF to an ON condition.
Claim 2
Dependent Claim
174 words
The combination comprising: first and second IGFETs of complementary conductivity type, each IGFET having source and drain electrodes defining the ends of a conduction path and a control electrode; a signal input terminal, a signal output terminal, and first and second power terminals for the application therebetween of an operating potential; means connecting the control electrodes of said first and second IGFETs to said signal input terminal; means connecting the drain electrodes of said first and second IGFETs to said signal output terminal; a controllable impedance means connected between said source of said first IGFET and said first power terminal, said controllable impedance means normally providing a relatively high impedance path when said first IGFET is turned on; means connecting said source of said second IGFET to said second power terminal; and pulse generating means coupled between said signal output terminal and said controllable impedance means for momentarily placing said controllable impedance means in a relatively low impedance condition in response to said first IGFET being driven from an OFF to an ON condition.
Claim 3
Dependent Claim
104 words
The combination as claimed in claim 1 wherein said controllable impedance means includes third and fourth IGFETs, of same conductivity type as said first IGFET, having their conduction paths connected in parallel between the source of said first IGFET and said first power terminal, said third IGFET being a relatively small geometry device of relatively high impedance when turned-on, with its gate electrode connected to said signal input terminal, and said fourth IGFET being a relatively large geometry, relatively low impedance device when turned on, and wherein said pulse generating means is connected at it's output to the control electrode of said fourth IGFET.
Claim 4
Dependent Claim
50 words
The combination as claimed in claim 2 further including means for applying first and second voltages to said first and second power terminals, respectively, and said signal input terminal being receptive to binary input signals one binary condition having a wide range of values between said first and second voltages.
Claim 5
Dependent Claim
140 words
The combination as claimed in claim 3 wherein said pulse generating means includes: (a) a fifth IGFET of first conductivity type and sixth and seventh IGFETs of second conductivity type, wherein the conduction path of said fifth IGFET is connected between said first power terminal and the control electrode of said fourth IGFET, wherein the conduction paths of said sixth and sevenths IGFETs are connected in series between the control electrode of said fourth IGFET and said second power terminal; (b) N inverters connected in cascade, where N is an odd number, the input of the first inverter being connected to said signal output terminal and the output of the Nth inverter being connected to the control electrodes of said fifth and sixth IGFETs; and (c) means connecting said signal output terminal to the control electrode of said seventh IGFET.
Claim 6
Dependent Claim
41 words
The combination as claimed in claim 1 wherein said signal output terminal is characterized as high impedance capacitive node, and wherein the capacitance at the source of said first IGFET is substantially greater than the capacitance at said signal output terminal.
Claim 7
Dependent Claim
21 words
The combination as claimed in claim 1 wherein said first and second IGFETs are of comparable impedance under like turn-on conditions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-13 | 1987-09-12 | 1988-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-13 | 1991-09-12 | 1992-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-13 | 1995-09-12 | 1996-03-13 | $7700.00 | Window Closed / Lapsed |