CMOS Source/drain implant process without compensation of polysilicon doping

Claim 1

A process for forming both first-conductivity-type-channel and second-conductivity-type-channel transistors in respective selected areas of a semiconductor surface, said transistors each respectively comprising a gate, a source, and a drain, said process comprising the steps of: providing a layer of doped first-conductivity-type polysilicon atop said semiconductor surface; applying a patterned etch mask layer atop said polysilicon layer, said patterned etch mask layer overlying the respective selected locations of said respective gates of said transistors; anisotropically etching said polysilicon layer except where said polysilicon layer is covered by a portion of said patterned etch mask layer; implanting a second-conductivity-type dopant in the respective desired locations both of the respective sources and drains both of said second-conductivity-type-channel transistors and one of said first-conductivity-type-channel transistors, said patterned etch mask layer not being removed before said second-type implanting step; and implanting a first-conductivity-type dopant in the respective desired locations of said respective sources and drains of said first-type-channel transistors, said first-type dopant being applied at a higher dose than said second-type dopant; wherein said first- and second-type dopants are such that the presence of said first-type dopant within said semiconductor surface reduces the diffusivity of said second-type dopant.