Process for fabricating insulated gate field effect transistor structure

Claim 1

IN A PROCESS OF FABRICATING A COMPLEMENTARY INSULATED GATE FIELD EFFECT TRANSISTOR STRUCTURE WHEREIN N-CHANNEL AND P-CHANNEL DEVICES ARE FABRICATED IN THE SAME SEMICONDUCTOR SUBSTRATE INCLUDING THE STEPS OF FORMING A WELL OF A FIRST CONDUCTIVELY TYPE IN A SUBSTRATE OF A SECOND AND OPPOSITE CONDUCTIVITY TYPE, FORMING A CONDUCTOR-INSULATOR-SEMICONDUCTOR FIELD EFFECT DEVICE HAVING A SECOND CHANNEL CONDUCTIVITY TYPE WITHIN SAID WELL AND FORMING A CONDUCTOR-INSULATOR-SEMICONDUCTOR FIELD EFFECTDEVICE HAVING A FIRST CHANNEL CONDUCTIVITY TYPE IN SAID SUBSTRATE, THE IMPROVEMENT COMPRISING: FORMING THE SOURCE/DRAIN REGIONS OF SAID CONDUCTOR-INSULATOR-SEMICONDUCTOR DEVICES BY: INTRODUCING AN IMPURITY OF A FIRST CONDUCTIVITY TYPE INTO THE SOURCE DRAIN IN REGIONS OF BOTH OF SAID DEVICES, AND INTRODUCING AN IMPURITY OF A SECOND CONDUCTIVITY TYPE OPPOSITE OF SAID FIRST CONDUCTIVITY TYPE INTO THE SOURCE DRAIN REGIONS OF SAID DEVICE HAVING SAID SECOND CHANNEL CONDUCTIVITY TYPE, THE CONCENTRATIONOF SAID IMPURITY OF SAID SECOND CONDUCTIVITY TYPE IN SAID SOURCE DRAIN REGIONS BEING GREATER THAN THE CONCENTRATION OF SAID IMPURITY OF SAID FIRST CONDUCTIVITY TYPE SO THAT THE IMPURITY OF SAID SECOND CONDUCTIVITY TYPE TO PRODUCE IMPURITY OF SAID FIRST CONDUCTIVITY TYPE TO PRODUCE SOURCELDRAIN REGIONSOF SAID SECOND CONDUCTIVITY TYPE.