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US4226650A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of reducing emitter dip in transistors utilizing specifically paired dopants

Assignee: Individual
•
Filing: 1978-05-30
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Granted: 1980-10-07
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Expires: 1998-05-30
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Abstract

Abstract A semiconductor device comprising an N type collector layer formed in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity material of which the energy of combination with vacancies is great and boron which is a P type impurity material, and an N type emitter layer which is so formed as to be surrounded by this P type base layer and forms a transistor together with the N type collector layer and the P type base layer and which contains the N type impurity materials phosphorus and arsenic. Arsenic or antimony or the like, which are N type impurity materials of which the energy of combination with vacancies is great are diffused in the P type base layer.

Inventors

  • 👤 Kouichi Takahashi
  • 👤 Hidekuni Ishida
  • 👤 Toshio Yonezawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 07:07
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10D62/834; H10D10/00; H10D10/40; H10D10/421; H10D62/10; H10D62/13; H10D62/133; H10D62/17; H10D62/177; H10P; H10P32/00; Y; Y10; Y10S; Y10S438/00; Y10S438/965

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 221 words
A method of manufacturing a semiconductor device comprising: providing an N type collector layer in an N type silicon semiconductor wafer having a substantially flat surface; diffusing an N type impurity having a high energy of combination with vacancies and boron which is a P type impurity material through a first opening in a first insulating layer covering said N type collector layer such that a P type base layer in contact with said N type collector layer having a PN junction extending to said surface is formed, said P type base layer having a substantially uniform P type impurity concentration distribution in the direction of depth of said layer; covering said N type collector layer and said P type base layer with a second insulating layer; forming a second opening in said second insulating layer, said second opening being smaller than said first opening in said first insulating layer; and diffusing phosphorus and arsenic which are N type impurity materials through said second opening in said second insulating layer into said P type base layer so that an N type emitter layer is formed which is in contact with said P type base layer having a PN junction extending to said surface and which constitutes a transistor together with said N type collector layer and said P type base layer.
Claim 2
Independent Claim 221 words
A method of manufacturing a semiconductor device comprising: providing an N type collector layer in an N type silicon semiconductor wafer having a substantially flat surface; diffusing an N type impurity having a high energy of combination with vacancies and boron which is a P type impurity material through a first opening in a first insulating layer covering said N type collector layer such that a P type base layer in contact with said N type collector layer having a PN junction extending to said surface is formed, said P type base layer having a substantially uniform P type impurity concentration distribution in the direction of depth of said layer; covering said N type collector layer and said P type base layer with a second insulating layer; forming a second opening in said second insulating layer, said second opening being smaller than said first opening in said first insulating layer; and diffusing phosphorus and arsenic which are N type impurity materials through said second opening in said second insulating layer into said P type base layer so that an N type emitter layer is formed which is in contact with said P type base layer having a PN junction extending to said surface and which constitutes a transistor together with said N type collector layer and said P type base layer.
Claim 3
Independent Claim 303 words
A method of manufacturing a semiconductor device which comprises the steps of: providing an N type collector layer in an N type silicon semiconductor wafer having a substantially flat surface; coating said N type collector layer with a first oxide film layer; forming a first opening in said first oxide film layer such that a portion of the surface of said N type collector layer is exposed; depositing a layer doped with an N type impurity having a high energy of combination with vacancies on said N type collector layer exposed by said first opening; diffusing said N type impurity from said N type impurity doped layer into said N type collector layer; removing said N type impurity doped layer from said N type collector layer; depositing a boron doped layer on said N type collector layer exposed by said first opening; diffusing boron from said boron doped layer into said N type collector layer such that a P type base layer in contact with said N type collector layer having a PN junction extending to said surface is formed; removing said boron doped layer from said N type collector; covering said N type collector layer and said P type base layer with a second oxide film layer; forming a second opening in said second oxide film layer, said second opening being smaller than said first opening in said first oxide film layer; and diffusing phosphorus and arsenic which are N type impurities through said second opening in said second oxide layer into said P type base layer such that an N type emitter layer is formed which is in contact with said P type base layer having a PN junction extending to said surface and which constitutes a transistor together with said N type collector layer and said P type base layer.
Claim 4
Independent Claim 303 words
A method of manufacturing a semiconductor device which comprises the steps of: providing an N type collector layer in an N type silicon semiconductor wafer having a substantially flat surface; coating said N type collector layer with a first oxide film layer; forming a first opening in said first oxide film layer such that a portion of the surface of said N type collector layer is exposed; depositing a layer doped with an N type impurity having a high energy of combination with vacancies on said N type collector layer exposed by said first opening; diffusing said N type impurity from said N type impurity doped layer into said N type collector layer; removing said N type impurity doped layer from said N type collector layer; depositing a boron doped layer on said N type collector layer exposed by said first opening; diffusing boron from said boron doped layer into said N type collector layer such that a P type base layer in contact with said N type collector layer having a PN junction extending to said surface is formed; removing said boron doped layer from said N type collector; covering said N type collector layer and said P type base layer with a second oxide film layer; forming a second opening in said second oxide film layer, said second opening being smaller than said first opening in said first oxide film layer; and diffusing phosphorus and arsenic which are N type impurities through said second opening in said second oxide layer into said P type base layer such that an N type emitter layer is formed which is in contact with said P type base layer having a PN junction extending to said surface and which constitutes a transistor together with said N type collector layer and said P type base layer.
Claim 5
Dependent Claim 30 words
A method of manufacturing a semiconductor device as recited in claim 1 or claim 2 wherein: said N type impurity having a high energy of combinaton with vacancies is arsenic.
Claim 6
Dependent Claim 30 words
A method of manufacturing a semiconductor device as recited in claim 1 or claim 2 wherein: said N type impurity having a high energy of combination with vacancies is antimony.

References Cited (Backward Citations)

US3707410A Cited
US3852127A Cited
US3507715A Cited
US3493443A Cited
US3635772A Cited
US3649387A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1983-10-07 1984-04-07 1984-10-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1987-10-07 1988-04-07 1988-10-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1991-10-07 1992-04-07 1992-10-07 $7700.00 Window Closed / Lapsed

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