Method for fabricating improved complementary metal oxide semiconductor devices

Claim 2

A process for forming a high packing density CMOS integrated circuit device from a structure including a body of a semiconductor material having a first active region of a first conductivity type, a second active region of a second conductivity type, and a thin silicon dioxide layer formed on said body encompassing a gate region within each of said active regions, said process comprising the steps of: forming a layer of polysilicon over said thin silicon dioxide layer; patterning said polysilicon into gate electrodes corresponding to said first and second active regions; doping the substrate independently of said gate electrodes to form the source and drain of a first conductivity type in said second active region and a source and drain of the second conductivity type in said first active region such that said sources and drains are aligned with their corresponding gates; doping said polysilicon gates with impurities of a single conductivity type independently of said sources and drains whereby said device is free of dopant penetration from said gates into said substrate through said thin oxide layer.

Claim 3

The process as recited in claim 1 wherein the step of patterning the polysilicon into gate electrodes comprises the steps of: forming a silicon dioxide-silicon nitride dual mask over the polysilicon layer defining the gate electrodes therein; and forming the layer of polysilicon in the presence of the dual mask into gate electrodes.

Claim 4

The process as recited in claim 1 further comprising the steps of: before patterning the polysilicon layer into gates doping said polysilicon layer with impurities of a single conductivity type to a low level of conductivity; forming a silicon dioxide-silicon nitride mask over the polysilicon layer defining gate electrodes and resistors therein; patterning the polysilicon in the presence of the oxide-nitride mask into resistors simultaneously with the patterning of the polysilicon into gate electrodes; and forming a mask over the resistors for protecting said resistors during doping of the gate electrodes.

Claim 5

The process as recited in claim 2 wherein doping said gates comprises the steps of: forming a relatively thick silicon dioxide implantation barrier over the sources and drains to protect said sources and drains from further doping; removing said dual mask over each gate electrode; and implanting impurities of a single conductivity into the exposed polysilicon layer of said gate electrodes.

Claim 6

The process as recited in claim 3 wherein the mask over the resistors is a layer of either polysilicon or silicon nitride.

Claim 7

A process for forming a high packing density CMOS integrated circuit from a structure comprising a body of semiconductor material having a first active region and a second active region, respectively, with a p-well formed in the first active region and a 400-700 Angstroms thin silicon dioxide layer formed over said active regions, said process comprising the following steps essentially in the sequence set forth: forming a polysilicon layer over the silicon dioxide layers and over the body of the semiconductor material; doping said polysilicon layer with n-type impurities to a relatively low level of conductivity suitable for forming therefrom polysilicon resistors; forming an oxidation and implantation mask over the polysilicon layer; patterning the polysilicon layer by using the oxidation and implantation mask into polysilicon gate structures corresponding to the first and second active regions, polysilicon conductor structures and polysilicon resistor structures; covering the side surfaces of said gate structures, conductor structures and resistor structures with a layer of silicon dioxide; forming a mask over said polysilicon resistor structures; implanting n-type and p-type impurities in source and drain regions defined in the first and second active regions, respectively, by the respective polysilicon gate structures; thermally oxidizing the substrate forming a relatively thick silicon dioxide implantation barrier over the source and drain regions in said first and second active regions; removing said oxidation and implantation mask over the polysilicon gate structures and polysilicon conductor structures to form polysilicon gates and polysilicon conductors respectively; simultaneously implanting the polysilicon gates and polysilicon conductors with n-type impurities to a relatively high level of conductivity whereby is created a CMOS device free of dopant penetration from said gates into said substrate via said thin oxide.

Claim 8

A process for forming a high packing density CMOS integrated circuit from a structure comprising a body of semiconductor material having a first active region and a second active region, respectively, with a p-well formed in the first active region and a 400-700 Angstroms thin silicon dioxide layer formed over said active regions, said process comprising the following steps essentially in the sequence set forth: forming a polysilicon layer over the silicon dioxide layers and over the body of the semiconductor material; doping said polysilicon layer with n-type impurities to a relatively low level of conductivity suitable for forming therefrom polysilicon resistors; forming an oxidation and implantation mask over the polysilicon layer; patterning the polysilicon layer by using the oxidation and implantation mask into polysilicon gate structures corresponding to the first and second active regions, polysilicon conductor structures and polysilicon resistor structures; covering the side surfaces of said gate structures, conductor structures and resistor structures with a layer of silicon dioxide; forming a mask over said polysilicon resistor structures; implanting n-type and p-type impurities in source and drain regions defined in the first and second active regions, respectively, by the respective polysilicon gate structures; thermally oxidizing the substrate forming a relatively thick silicon dioxide implantation barrier over the source and drain regions in said first and second active regions; removing said oxidation and implantation mask over the polysilicon gate structures and polysilicon conductor structures to form polysilicon gates and polysilicon conductors respectively; simultaneously implanting the polysilicon gates and polysilicon conductors with n-type impurities to a relatively high level of conductivity whereby is created a CMOS device free of dopant penetration from said gates into said substrate via said thin oxide.

Claim 9

The process as recited in claim 6 wherein the oxidation and implantation mask over the polysilicon comprises a layer of silicon dioxide and a layer of silicon nitride.

Claim 10

The process as recited in claim 7 wherein the mask over the resistor structures is a layer of either polysilicon or silicon nitride.