US4328558A
Expired / Lapsed
US
⏱️ 0.0 years remaining
RAM Address enable circuit for a microprocessor having an on-chip RAM
Assignee: Motorola Solutions Inc
•
Filing: 1978-03-09
•
Granted: 1982-05-04
•
Expires: 1998-03-09
Abstract
Abstract A pulse generating circuit is coupled to an address decoder to provide the address enable signal to the address decoder. An input pulse is provided to the pulse generating circuit and the output of the pulse generating circuit is coupled to the address decoder. The output of the pulse generating circuit keeps the address decoder enabled until the trailing edge of the input pulse. Internal to the pulse generating circuit the input pulse is connected to a delay. The output of the delay is connected to a first NOR gate. Another input of the first NOR gate receives the input pulse. The output of the first NOR gate is connected to a second NOR gate. Another input of the second NOR gate also receives the input pulse. The output of the second NOR gate is the output of the pulse generating circuit which is coupled to the address decoder. The pulse generating circuit provides a momentary output pulse at the trailing edge of the input pulse to momentarily inhibit the address decoder. The pulse generating circuit is particularly useful, in a microprocessor having an on-chip RAM, to inhibit the RAM address decoder at the trailing edge of a signal derived from a microprocessor clock thereby virtually eliminating instability problems of the RAM.
Inventors
- 👤 Fuad H. Musa
- 👤 Pern Shaw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:04
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7842; G06F15/786
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
193 words
A pulse generating circuit for generating a pulse to temporarily inhibit an address decoder, the generating circuit being a portion of a microprocessor having said address decoder, the circuit having an input and an output, comprising: means for producing an electrical delay, the means being coupled to the input of the circuit and providing an output; a first logic gate having at least a first and a second input and an output, the first input of the first logic gate being coupled to the output of the means for producing said electrical delay, the second input to the first logic gate being coupled to the input of the circuit; and a second logic gate having at least a first and a second input, the first input of the second logic gate being coupled to the output of the first logic gate and the second input to the second logic gate being coupled to the input of the circuit to at said output of the generating circuit provide the pulse to temporarily inhibit the address decoder upon occurrence of the trailing edge of a microprocessor control pulse received at the input of the circuit.
Claim 2
Dependent Claim
193 words
A pulse generating circuit for generating a pulse to temporarily inhibit an address decoder, the generating circuit being a portion of a microprocessor having said address decoder, the circuit having an input and an output, comprising: means for producing an electrical delay, the means being coupled to the input of the circuit and providing an output; a first logic gate having at least a first and a second input and an output, the first input of the first logic gate being coupled to the output of the means for producing said electrical delay, the second input to the first logic gate being coupled to the input of the circuit; and a second logic gate having at least a first and a second input, the first input of the second logic gate being coupled to the output of the first logic gate and the second input to the second logic gate being coupled to the input of the circuit to at said output of the generating circuit provide the pulse to temporarily inhibit the address decoder upon occurrence of the trailing edge of a microprocessor control pulse received at the input of the circuit.
Claim 3
Dependent Claim
25 words
The circuit of claim 1 wherein the means for producing said electrical delay comprises a series of inverters coupled together to provide the electrical delay.
Claim 4
Dependent Claim
23 words
The pulse generating circuit of claim 2 wherein the means for producing said delay includes an even number of inverters coupled in series.
Claim 5
Dependent Claim
55 words
The pulse generating circuit of claim 3 wherein the pulse to temporarily inhibit said address decoder has a duration which is set by the delay obtained from the means for producing said electrical delay, and wherein the delay obtained from the means for producing said electrical delay is dependent upon physical size of the inverters.
Claim 6
Dependent Claim
169 words
A pulse generating circuit coupled to an address decoder to provide an address enable signal to the address decoder, the address decoder being coupled to address lines of a random access memory, the pulse generating circuit comprising: means for providing a delay to an input pulse, the means for providing said delay having an output; a first logic gate coupled to the output of the means for providing said delay and also having at least an input to receive the input pulse and having an output; and a second logic gate coupled to the output of the first logic gate and also having at least an input coupled to the input pulse, the second logic gate providing at the output thereof the address enable signal to the address decoder until occurrence of the trailing edge of the input pulse and then generating a inhibiting pulse to the address decoder to cause the address decoder to set the address lines to a nonaddressing state in response to the inhibiting pulse.
Claim 7
Dependent Claim
169 words
A pulse generating circuit coupled to an address decoder to provide an address enable signal to the address decoder, the address decoder being coupled to address lines of a random access memory, the pulse generating circuit comprising: means for providing a delay to an input pulse, the means for providing said delay having an output; a first logic gate coupled to the output of the means for providing said delay and also having at least an input to receive the input pulse and having an output; and a second logic gate coupled to the output of the first logic gate and also having at least an input coupled to the input pulse, the second logic gate providing at the output thereof the address enable signal to the address decoder until occurrence of the trailing edge of the input pulse and then generating a inhibiting pulse to the address decoder to cause the address decoder to set the address lines to a nonaddressing state in response to the inhibiting pulse.
Claim 8
Dependent Claim
17 words
The pulse generating circuit of claim 5 wherein the first and second logic gates are NOR gates.
Claim 9
Dependent Claim
26 words
The pulse generating circuit of claim 6 wherein the means for providing a delay comprises said plurality of inverters arranged in series to provide the delay.
Claim 10
Dependent Claim
50 words
The pulse generating circuit of claim 5 wherein the first logic gate also receives a third input derived from a memory enable signal so that the output of said first logic gate can be gated by said memory enable signal so as to effectively gate the address enable signal therewith.
References Cited (Backward Citations)
US2984789A
Cited
US3229258A
Cited
US3619790A
Cited
US3624519A
Cited
US3628065A
Cited
US3792355A
Cited
US3728635A
Cited
US3736567A
Cited
US3737637A
Cited
US3735270A
Cited
US3862440A
Cited
US3792362A
Cited
US3925735A
Cited
US4061975A
Cited
US3947829A
Cited
US3894247A
Cited
US3919695A
Cited
US3970944A
Cited
US3969706A
Cited
US4050096A
Cited
US3959781A
Cited
US4063308A
Cited
US4122361A
Cited
US4035663A
Cited
US4069429A
Cited
US4110639A
Cited
US4104860A
Cited
US4063117A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-03 | 1985-11-02 | 1986-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-03 | 1989-11-02 | 1990-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-03 | 1993-11-02 | 1994-05-04 | $7700.00 | Window Closed / Lapsed |