Patent DE630529C successfully refreshed from Google Patents.
US3628065A
Expired / Lapsed
US
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Clock pulse generator
Assignee: AT&T Inc
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Filing: 1970-10-27
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Granted: 1971-12-14
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Expires: 1990-10-27
Abstract
Abstract A variable speed two-pulse clock circuit or pulse generator is formed by a group of time delay sections connected in cascade in combination with logic control circuitry. Each time delay section is formed from a combination of IGFETS and MOS capacitors and, hence, the system lends itself to production by integrated circuit fabrication techniques.
Inventors
- 👤 Donald Gifford Hill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:13
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/156; H03K5/13; H03K5/133; H03K5/15; H03K5/151; H03K5/1515; H03K2005/00013; H03K2005/0015; H03K2005/00195
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
238 words
Apparatus for generating a first train of pulses of one polarity and a second train of pulses of the opposite polarity, each of the pulses in said second train corresponding in time to a preselected portion of a respective one of the pulses in said first train comprising, in combination, a first time delay circuit for providing a delay between the inception of a pulse in said first train and the inception of a corresponding pulse in said second train, a second time delay circuit for establishing the duration of each pulse in said second train as an included part of the duration of each corresponding pulse in said first train, a third time delay circuit for establishing the pulse repetition rate of pulses in said first train and hence, indirectly, in said second train, a fourth time delay circuit for providing a delay between the termination of each pulse in said second train and the termination of each corresponding pulse in said first train, first output logic circuitry in combination with said first and second delay circuits for producing pulses in said first train, clock logic circuitry for supplying periodic inputs to said first logic circuit and to a second logic circuit and said second logic circuit combining outputs from said clock circuit and from said fourth time delay circuit to produce pulses in said second train, all of said time delay circuits being connected in cascade.
Claim 2
Dependent Claim
238 words
Apparatus for generating a first train of pulses of one polarity and a second train of pulses of the opposite polarity, each of the pulses in said second train corresponding in time to a preselected portion of a respective one of the pulses in said first train comprising, in combination, a first time delay circuit for providing a delay between the inception of a pulse in said first train and the inception of a corresponding pulse in said second train, a second time delay circuit for establishing the duration of each pulse in said second train as an included part of the duration of each corresponding pulse in said first train, a third time delay circuit for establishing the pulse repetition rate of pulses in said first train and hence, indirectly, in said second train, a fourth time delay circuit for providing a delay between the termination of each pulse in said second train and the termination of each corresponding pulse in said first train, first output logic circuitry in combination with said first and second delay circuits for producing pulses in said first train, clock logic circuitry for supplying periodic inputs to said first logic circuit and to a second logic circuit and said second logic circuit combining outputs from said clock circuit and from said fourth time delay circuit to produce pulses in said second train, all of said time delay circuits being connected in cascade.
Claim 3
Dependent Claim
40 words
Apparatus in accordance with claim 1 wherein each of said time delay circuits comprises a plurality of IGFET devices and a timing capacitor, the discharge path of said capacitor being through a high-impedance path of one of said IGFET devices.
Claim 4
Dependent Claim
37 words
Apparatus in accordance with claim 1 wherein said first logic circuit includes first input means from the output of said first time delay circuit and second input means from the output of said second time delay circuit.
Claim 5
Dependent Claim
35 words
Apparatus in accordance with claim 1 wherein said second logic circuit includes first input means from the output of said fourth logic circuit and second input means from the output of said clock logic circuitry.
Claim 6
Dependent Claim
169 words
A clock pulse generator for simultaneously generating a first pulse train of one polarity and a second pulse train of an opposite polarity, each of the pulses in said second train being of less duration than but included within the time period of a corresponding pulse in said first train, said generator comprising, in combination, a plurality of substantially identical cascade-connected time delay circuits each including a respective timing capacitor and a relatively high-impedance IGFET disCharge path therefor, first, second and third logic circuits for establishing the operating sequence and timing control relations among said time delay circuits, said first logic circuit having inputs derived from the outputs of two of said time delay circuits and an output establishing the time limits of the pulses of said second train, said second logic circuit having inputs derived from the output of one of said time delay circuits and from the output of said third logic circuit and an output establishing the time limits of the pulses of said first train.
Claim 7
Dependent Claim
169 words
A clock pulse generator for simultaneously generating a first pulse train of one polarity and a second pulse train of an opposite polarity, each of the pulses in said second train being of less duration than but included within the time period of a corresponding pulse in said first train, said generator comprising, in combination, a plurality of substantially identical cascade-connected time delay circuits each including a respective timing capacitor and a relatively high-impedance IGFET disCharge path therefor, first, second and third logic circuits for establishing the operating sequence and timing control relations among said time delay circuits, said first logic circuit having inputs derived from the outputs of two of said time delay circuits and an output establishing the time limits of the pulses of said second train, said second logic circuit having inputs derived from the output of one of said time delay circuits and from the output of said third logic circuit and an output establishing the time limits of the pulses of said first train.
Claim 8
Dependent Claim
97 words
Apparatus in accordance with claim 5 wherein each of said time delay circuits comprises a first pair of IGFET devices forming a voltage divider, a second pair of IGFET devices wherein one provides a discharge path for a timing capacitor and the other controls the impedance level of said path, and a third pair of IGFET devices wherein one provides an output signal developed from the discharging of said capacitor and the other operates as a load device, each of said pairs being connected in substantially parallel circuit configuration with each of the other of said pairs.
Claim 9
Dependent Claim
34 words
Apparatus in accordance with claim 6 including a first control voltage source connected to said load device IGFET and a second control voltage source connected to each of said second pair of IGFET devices.
Claim 10
Dependent Claim
36 words
Apparatus in accordance with claim 7 including means for applying an input signal from the output of said third logic circuit to said IGFET device of said second pair controlling the impedance level of said path.
Claim 11
Dependent Claim
18 words
Apparatus in accordance with claim 7 wherein said third logic circuit generates a square wave pilot signal output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-13 | 1975-06-14 | 1975-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-13 | 1979-06-14 | 1979-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-13 | 1983-06-14 | 1983-12-14 | $7700.00 | Window Closed / Lapsed |