US4035663A
Expired / Lapsed
US
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Two phase clock synchronizing method and apparatus
Assignee: Boeing North American Inc
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Filing: 1976-09-01
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Granted: 1977-07-12
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Expires: 1996-09-01
Abstract
Abstract A circuit for detecting and synchronizing an incoming signal to a reference clock wherein the incoming signal has a slightly lower frequency and may be variable in frequency with respect to the reference clock frequency. The output from this synchronizer will be stable during the first half-cycle of the reference clock and may vary during the second half-cycle of the reference clock.
Inventors
- 👤 Kevin C. Stodola
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:04
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
202 words
The method of synchronizing an incoming signal comprising a train of pulses to a reference clock comprising the steps of: storing a signal indicative of the logic level of said incoming signal at the end of a second half-cycle of a reference clock as a first signal; storing a signal indicative of the logic level of said incoming signal occurring during a following first half-cycle of said reference clock as a second signal; storing a signal indicative of the logic level of said incoming signal at the end of the last previous second half-cycle of said reference clock as a third signal; storing a signal indicative of the logic level of said incoming signal at the end of the last previous first half-cycle of said reference clock as a fourth signal; Nanding said second and third signals to provide a fifth signal; passing said fifth signal as a sixth signal during each first half-cycle of said reference clock; storing said sixth signal during the following second half-cycle of said reference clock; Nanding said first and fourth signals to provide a seventh signal; and Nanding said sixth and seventh signals to provide a synchronized output signal representative of the incoming train of pulses.
Claim 2
Independent Claim
202 words
The method of synchronizing an incoming signal comprising a train of pulses to a reference clock comprising the steps of: storing a signal indicative of the logic level of said incoming signal at the end of a second half-cycle of a reference clock as a first signal; storing a signal indicative of the logic level of said incoming signal occurring during a following first half-cycle of said reference clock as a second signal; storing a signal indicative of the logic level of said incoming signal at the end of the last previous second half-cycle of said reference clock as a third signal; storing a signal indicative of the logic level of said incoming signal at the end of the last previous first half-cycle of said reference clock as a fourth signal; Nanding said second and third signals to provide a fifth signal; passing said fifth signal as a sixth signal during each first half-cycle of said reference clock; storing said sixth signal during the following second half-cycle of said reference clock; Nanding said first and fourth signals to provide a seventh signal; and Nanding said sixth and seventh signals to provide a synchronized output signal representative of the incoming train of pulses.
Claim 3
Dependent Claim
343 words
Apparatus for synchronizing an incoming signal to a reference clock comprising, in combination: means for supplying an incoming signal comprising a train of pulses; means for supplying a reference clock signal having full cycles each comprising first and second half-cycles; means for storing a signal indicative of the logic level of said incoming signal at the end of a second half-cycle of the reference clock as a first signal; means for connecting the first two recited means to supply signals to the third recited means; means for outputting a signal indicative of the logic level of said incoming signal occurring during a first half-cycle of said reference clock as a second signal; means for connecting the first two recited means to said means for outputting; first storage means, connected to said means for storing, for storing a signal indicative of the logic level of said incoming signal at the end of the last previous second half-cycle of said reference clock as a third signal; second storage means, connected to said means for outputting, for storing a signal indicative of the logic level of said incoming signal at the end of the last previous first half-cycle of said reference clock as a fourth signal; first NAND gate means, connected to said means for outputting and to said first storage means, for receiving said second and third signals therefrom to provide a fifth signal; gating means connected to the output of said first NAND gate means, for passing said fifth signal during each second half-cycle of said reference clock and for storing said fifth signal during the following first half-cycle of said reference clock as a sixth signal; second NAND gate means, connected to said means for storing and to said second storage means, for receiving said first and fourth signals therefrom to provide a seventh signal; and third NAND gate means connected to said second NAND gate means and to said gating means for receiving said sixth and seventh signals therefrom to provide a synchronized output signal representative of the incoming train of pulses.
Claim 4
Dependent Claim
343 words
Apparatus for synchronizing an incoming signal to a reference clock comprising, in combination: means for supplying an incoming signal comprising a train of pulses; means for supplying a reference clock signal having full cycles each comprising first and second half-cycles; means for storing a signal indicative of the logic level of said incoming signal at the end of a second half-cycle of the reference clock as a first signal; means for connecting the first two recited means to supply signals to the third recited means; means for outputting a signal indicative of the logic level of said incoming signal occurring during a first half-cycle of said reference clock as a second signal; means for connecting the first two recited means to said means for outputting; first storage means, connected to said means for storing, for storing a signal indicative of the logic level of said incoming signal at the end of the last previous second half-cycle of said reference clock as a third signal; second storage means, connected to said means for outputting, for storing a signal indicative of the logic level of said incoming signal at the end of the last previous first half-cycle of said reference clock as a fourth signal; first NAND gate means, connected to said means for outputting and to said first storage means, for receiving said second and third signals therefrom to provide a fifth signal; gating means connected to the output of said first NAND gate means, for passing said fifth signal during each second half-cycle of said reference clock and for storing said fifth signal during the following first half-cycle of said reference clock as a sixth signal; second NAND gate means, connected to said means for storing and to said second storage means, for receiving said first and fourth signals therefrom to provide a seventh signal; and third NAND gate means connected to said second NAND gate means and to said gating means for receiving said sixth and seventh signals therefrom to provide a synchronized output signal representative of the incoming train of pulses.
Claim 5
Dependent Claim
195 words
Apparatus for providing a synchronized output pulse train of a given frequency from a lower frequency incoming unsynchronized train of pulses comprising, in combination: first means for supplying a reference clock signal having full cycles each comprising first and second half-cycles; means for supplying an incoming signal comprising a train of pulses to be synchronized; first detection means for commencing an output whenever, between the end of the first half cycle and the end of the second half-cycle, the logic level of said incoming signal changes with respect to its logic level at the end of the previous second half-cycle; logic circuit means for continuing the output to the end of the first half-cycle following the commencement of said output; second detection means for commencing an output at the beginning of a second half-cycle whenever, between the end of the previous second half-cycle and the end of a present first half-cycle, the logic level of said incoming signal changes with respect to its logic level in the previous second half-cycle; and logic circuit means for continuing the output for a full cycle following the commencement of said output as generated by said second detection means.
Claim 6
Dependent Claim
195 words
Apparatus for providing a synchronized output pulse train of a given frequency from a lower frequency incoming unsynchronized train of pulses comprising, in combination: first means for supplying a reference clock signal having full cycles each comprising first and second half-cycles; means for supplying an incoming signal comprising a train of pulses to be synchronized; first detection means for commencing an output whenever, between the end of the first half cycle and the end of the second half-cycle, the logic level of said incoming signal changes with respect to its logic level at the end of the previous second half-cycle; logic circuit means for continuing the output to the end of the first half-cycle following the commencement of said output; second detection means for commencing an output at the beginning of a second half-cycle whenever, between the end of the previous second half-cycle and the end of a present first half-cycle, the logic level of said incoming signal changes with respect to its logic level in the previous second half-cycle; and logic circuit means for continuing the output for a full cycle following the commencement of said output as generated by said second detection means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-11 | 1981-01-10 | 1981-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-11 | 1985-01-10 | 1985-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-11 | 1989-01-10 | 1989-07-12 | $7700.00 | Window Closed / Lapsed |