US3619790A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for selectively suppressing a pulse in a pulse train
Assignee: Plessey Overseas Ltd
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Filing: 1970-03-13
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Granted: 1971-11-09
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Expires: 1990-03-13
Abstract
Abstract A circuit for selectively suppressing a pulse in a pulse train utilizing first and second bistable devices and first and second two input gates. The circuit normally permits the passage of a train of pulses from an input terminal, but upon the application of a command signal at a command terminal, a pulse of the train is suppressed without mutilating the other pulses, actual suppression being accomplished by the response of said second bistable device to the trailing edge of the pulses of said pulse train.
Inventors
- 👤 Richard N Brooksbank
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:03
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/156
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
262 words
An electric circuit for selectively suppressing a pulse in a pulse train in response to a command signal comprising first and second bistable devices both having stable rest and operated states; an input terminal at which said pulse train is received; a first two input gate having an input thereof coupled to said second bistable device for priming when said second bistable device is in the rest state; said first gate having its other input connected to the said input terminal so that the gate repeats said pulse train received at the input terminal while the second bistable device is in the rest state; a command terminal at which said command signal is received; a second two input gate having an input thereof coupled to said second bistable device for priming when said second bistable device is in the rest state, said second gate having its other input connected to said command terminal; means connecting the output of the secoNd gate and said first bistable device so that said first bistable device is switched to its operated state on the opening of the second gate; means connecting said input terminal and said second bistable device; means connecting said command terminal and said second bistable device so that said second bistable device is primed for switching to its operated state in response to the pulse train from said input terminal; and means connecting said first bistable device to said second bistable device so that the switching of the second bistable device is prevented while the first bistable device is in the rest state.
Claim 2
Dependent Claim
262 words
An electric circuit for selectively suppressing a pulse in a pulse train in response to a command signal comprising first and second bistable devices both having stable rest and operated states; an input terminal at which said pulse train is received; a first two input gate having an input thereof coupled to said second bistable device for priming when said second bistable device is in the rest state; said first gate having its other input connected to the said input terminal so that the gate repeats said pulse train received at the input terminal while the second bistable device is in the rest state; a command terminal at which said command signal is received; a second two input gate having an input thereof coupled to said second bistable device for priming when said second bistable device is in the rest state, said second gate having its other input connected to said command terminal; means connecting the output of the secoNd gate and said first bistable device so that said first bistable device is switched to its operated state on the opening of the second gate; means connecting said input terminal and said second bistable device; means connecting said command terminal and said second bistable device so that said second bistable device is primed for switching to its operated state in response to the pulse train from said input terminal; and means connecting said first bistable device to said second bistable device so that the switching of the second bistable device is prevented while the first bistable device is in the rest state.
References Cited (Backward Citations)
US2636133A
Cited
US3007115A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-08 | 1975-05-10 | 1975-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-08 | 1979-05-10 | 1979-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-08 | 1983-05-10 | 1983-11-09 | $7700.00 | Window Closed / Lapsed |