Storage cell simulation for generating a reference voltage for semiconductor stores in mtl technology

Claim 2

A solid state reference voltage generator circuit structure for a solid state memory fabricated in a P-type substrate of semiconductor material, said solid-state reference voltage generator circuit structure comprising: an N-type epitaxial layer formed on a surface of said P-type substrate; an N-type subcollector region formed in said P-type substrate beneath said epitaxial layer; a plurality of elongated P-type regions formed in said epitaxial layer, said plurality of elongated P-type regions being co-extensive one to the other and equally spaced one from another; and means for electrically isolating said plurality of elongated P-type regions formed in said epitaxial layer.

Claim 3

A simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology, said simulated storage cell structure comprising: a P-type semiconductor substrate; an N-type semiconductor epitaxial layer formed on a surface of said P-type substrate; an N+ type subcollector semiconductor region formed in said P-type substrate beneath said epitaxial layer; a plurality of elongated P-type semiconductor regions formed in a portion of said epitaxial layer; an additional N+ type semiconductor region integral with said N+ type subcollector region, said additional N+ type semiconductor region and said N+ type semiconductor subcollector region together fully encompassing said portion of said epitaxial layer containing said plurality of elongated P-type semiconductor regions; current source means connected to predetermined ones of said plurality of elongated P-type semiconductor regions formed in said portion of said epitaxial layer; and output circuit means connected in common to other predetermined ones of said plurality of elongated P-type semiconductor regions, said additional N+ type semiconductor region and said N+ type semiconductor subcollector region.

Claim 4

A simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology, said simulated storage cell structure comprising: a P-type semiconductor substrate; an N-type semiconductor epitaxial layer formed on a surface of said P-type substrate; an N+ type subcollector semiconductor region formed in said P-type substrate beneath said epitaxial layer; a plurality of elongated P-type semiconductor regions formed in a portion of said epitaxial layer; an additional N+ type semiconductor region integral with said N+ type subcollector region, said additional N+ type semiconductor region and said N+ type semiconductor subcollector region together fully encompassing said portion of said epitaxial layer containing said plurality of elongated P-type semiconductor regions; current source means connected to predetermined ones of said plurality of elongated P-type semiconductor regions formed in said portion of said epitaxial layer; and output circuit means connected in common to other predetermined ones of said plurality of elongated P-type semiconductor regions, said additional N+ type semiconductor region and said N+ type semiconductor subcollector region.

Claim 5

A simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology, as recited in claim 1, where said plurality of elongated P-type regions consists of an odd integer number of elongated P-type regions and wherein said predetermined ones connected to said current source means constitutes alternate ones of said odd integer number of elongated P-type regions.

Claim 6

A simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology, as recited in claim 13, wherein at least one of said plurality of elongated P-type semiconductor regions is "floating" (not connected to said current source means nor to said output circuit means).

Claim 7

A simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology, said simulated storage cell structure comprising: a P-type semiconductor substrate; an N-type semiconductor epitaxial layer formed on a surface of said P-type substrate; an N+ type subcollector semiconductor region formed in said P-type substrate beneath said epitaxial layer; a plurality of elongated P-type semiconductor regions formed in a portion of said epitaxial layer; an isolation region integral with said N+ type subcollector region, said isolation region and said N+ type semiconductor subcollector region together fully encompassing said portion of said epitaxial layer containing said plurality of elongated P-type semiconductor regions; potential source means connected to predetermined ones of said plurality of elongated P-type semiconductor regions formed in said portion of said epitaxial layer; and output circuit means connected in common to other predetermined ones of said plurality of elongated P-type semiconductor regions, and said N+ type semiconductor subcollector region.

Claim 8

A simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology, said simulated storage cell structure comprising: a P-type semiconductor substrate; an N-type semiconductor epitaxial layer formed on a surface of said P-type substrate; an N+ type subcollector semiconductor region formed in said P-type substrate beneath said epitaxial layer; a plurality of elongated P-type semiconductor regions formed in a portion of said epitaxial layer; an isolation region integral with said N+ type subcollector region, said isolation region and said N+ type semiconductor subcollector region together fully encompassing said portion of said epitaxial layer containing said plurality of elongated P-type semiconductor regions; potential source means connected to predetermined ones of said plurality of elongated P-type semiconductor regions formed in said portion of said epitaxial layer; and output circuit means connected in common to other predetermined ones of said plurality of elongated P-type semiconductor regions, and said N+ type semiconductor subcollector region.

Claim 9

A simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology, as recited in claim 5, where said plurality of elongated P-type regions consists of an odd integer number of elongated P-type regions and wherein said predetermined ones connected to said potential source means constitutes alternate ones of said odd integer number of elongated P-type regions.