Memory cell circuit and semiconductor structure therefore

Claim 2

A memory cell comprising: (a) a word line; (b) a pair of bit lines; (c) a pair of current sources comprising a pair of transistors each having an emitter coupled to a corresponding one of said pair of bit lines, a base coupled to said word line, and a collector terminal; (d) bistable circuit means comprising a pair of switching transistors each having a collector terminal coupled to a corresponding collector terminal of one of said current source transistors, a base terminal coupled to the collector terminal of the other of said pair of current source transistors, and an emitter terminal coupled to said word line, whereby said bistable circuit means assumes one stable state upon the application of a voltage on one bit line, and assumes another stable state upon the application of a voltage on the other bit line.

Claim 3

A memory cell as in claim 1 further characterized by said pair of current source transistors comprising PNP transistors.

Claim 4

A memory cell as in claim 1 further characterized by said pair of switching transistors comprising NPN transistors.

Claim 5

A semiconductor memory cell structure comprising: (a) a semiconductor substrate of a first conductivity type; (b) a buried layer formed in said substrate from semiconductor material of a second conductivity type to form a word line of said semiconductor memory cell; (c) an epitaxial layer formed over said buried layer from a semiconductor material of said first conductivity type, said epitaxial layer being partitioned into two halves by an isolation barrier; (d) each half of said epitaxial layer comprising: (i) a first region of semiconductor material of said second conductivity type, (ii) a second region of semiconductor material of said first conductivity type, (iii) a third region of semiconductor material of said second conductivity type, and (iv) a fourth region of semiconductor material of said first conductivity type; (e) first electrical conducting means forming a first bit line and coupled to said second region in a first half of said epitaxial layer; (f) second electrical conducting means forming a second bit line and coupled to said second region and the second half of said epitaxial layer; (g) third electrical conducting means coupling said third region in the first half of said epitaxial layer with said fourth region in the second half of said epitaxial layer; and (h) fourth electrical conducting means coupling said fourth region in the first half of said epitaxial layer with said third region in the second half of said epitaxial layer.

Claim 6

A semiconductor memory cell structure comprising: (a) a semiconductor substrate of a first conductivity type; (b) a buried layer formed in said substrate from semiconductor material of a second conductivity type to form a word line of said semiconductor memory cell; (c) an epitaxial layer formed over said buried layer from a semiconductor material of said first conductivity type, said epitaxial layer being partitioned into two halves by an isolation barrier; (d) each half of said epitaxial layer comprising: (i) a first region of semiconductor material of said second conductivity type, (ii) a second region of semiconductor material of said first conductivity type, (iii) a third region of semiconductor material of said second conductivity type, and (iv) a fourth region of semiconductor material of said first conductivity type; (e) first electrical conducting means forming a first bit line and coupled to said second region in a first half of said epitaxial layer; (f) second electrical conducting means forming a second bit line and coupled to said second region and the second half of said epitaxial layer; (g) third electrical conducting means coupling said third region in the first half of said epitaxial layer with said fourth region in the second half of said epitaxial layer; and (h) fourth electrical conducting means coupling said fourth region in the first half of said epitaxial layer with said third region in the second half of said epitaxial layer.

Claim 7

A structure as in claim 4 further characterized by said isolation barrier comprising insulation material.

Claim 8

A structure as in claim 5 further characterized by said insulating material comprising silicon dioxide.

Claim 9

A structure as in claim 4 further characterized by said isolation barrier comprising a PN isolation junction.

Claim 10

A structure as in claim 4 further characterized by said first conductivity type comprising p-type semiconductor material.

Claim 11

A structure as in claim 4 further characterized by said second conductivity type comprising n-type semiconductor material.

Claim 12

A structure as in claim 4 further characterized by said first region comprising heavily-doped n-type semiconductor material.

Claim 13

A structure as in claim 4 further characterized by said buried layer comprising heavily-doped n-type semiconductor material.

Claim 14

A structure as in claim 4 further characterized by said fourth region comprising heavily-doped p-type semiconductor material.

Claim 15

A semiconductor memory array comprising N×M memory cell structures as defined in claim 4, wherein N is a positive integer representing the number of cells in a row of said array, and M is a positive integer representing the number of cells in a column of said array.

Claim 16

A semiconductor memory array as in claim 13, further characterized by each of said memory cells in said array being isolated from each adjacent cell by means of an isolation barrier.

Claim 17

A semiconductor memory array as in claim 14 further characterized by said isolation barrier comprising insulating material.

Claim 18

A semiconductor memory array as in claim 15 further characterized by said insulating material comprising silicon dioxide.

Claim 19

A semiconductor memory array as in claim 14 further characterized by said isolation barrier comprising a PN isolation junction.

Claim 20

A semiconductor memory array as in claim 14 further characterized by said isolation barrier between each cell in each row comprising a PN isolation junction, and between each cell in each column comprising insulating material.