US4122548A
Expired / Lapsed
US
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Memory storage array with restore circuit
Assignee: International Business Machines Corp
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Filing: 1977-10-07
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Granted: 1978-10-24
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Expires: 1997-10-07
Abstract
Abstract A memory storage system which utilizes semiconductor storage cells comprised of cross-coupled bipolar transistors arranged in a memory system array with an error reference circuit and a standby reference circuit that is controlled by a clock signal. The standby reference circuit and the error reference circuit are both coupled to the bit lines and selectively control a restore circuit that maintains, in the standby state, a selected potential on the bit lines such that short access times are realized and current is prevented from flowing into unselected cells when adjacent defective cells are being read or written.
Inventors
- 👤 Klaus Heuber
- 👤 Wilfried Klein
- 👤 Knut Najmann
- 👤 Friedrich Wernicke
- 👤 Siegfried Kurt Wiedmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:13
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/416; G11C11/411; G11C11/4113
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
107 words
A memory circuit comprising a pair of bit lines, bipolar memory cells coupled between the bit lines through semiconductor devices, and means for maintaining information stored in said cells, said maintaining means comprising a standby reference circuit, controlled by a clock, coupled to a reference line, an error reference circuit coupled to said standby reference circuit and to said reference line, and a restore circuit coupled to said reference line, said restore circuit comprising two current sources each of which are coupled to a respective one of said pair of bit lines and to said reference line through a respective one of a pair of semiconductor devices.
Claim 2
Dependent Claim
107 words
A memory circuit comprising a pair of bit lines, bipolar memory cells coupled between the bit lines through semiconductor devices, and means for maintaining information stored in said cells, said maintaining means comprising a standby reference circuit, controlled by a clock, coupled to a reference line, an error reference circuit coupled to said standby reference circuit and to said reference line, and a restore circuit coupled to said reference line, said restore circuit comprising two current sources each of which are coupled to a respective one of said pair of bit lines and to said reference line through a respective one of a pair of semiconductor devices.
Claim 3
Dependent Claim
17 words
The circuit of claim 1 wherein said semiconductor devices coupled to the memory cell are Schottky diodes.
Claim 4
Dependent Claim
16 words
The circuit of claim 2 wherein said semiconductor devices in said restore circuit are Schottky diodes.
Claim 5
Dependent Claim
54 words
The circuit of claim 1 wherein said standby reference circuit comprises a control transistor and a pair of serially connected transistors coupled to the reference line, the conductive state of said serially connected transistors being controlled by said control transistor, and the state of said control transistor being responsive to signals from said clock.
Claim 6
Dependent Claim
35 words
The circuit of claim 4 wherein the error reference circuit comprises a pair of serially connected transistors coupled to the reference line, one of said pair of serially connected transistors being connected as a diode.
Claim 7
Dependent Claim
26 words
The circuit of claim 5 wherein the standby reference circuit and the error reference circuit are both coupled to the reference line through a common transistor.
Claim 8
Dependent Claim
11 words
The circuit of claim 6 wherein said common transistor is saturated.
Claim 9
Dependent Claim
130 words
A memory circuit comprising a word line, a pair of bit lines, a bipolar memory cell coupled between the bit lines means coupled to the word line for selectively setting the word line at first and second voltage levels, said second voltage level being at a magnitude lower than said first voltage level, and means for maintaining a selected voltage level on each of said bit lines including a pair of current sources each being coupled between a reference voltage and a respective one of said bit lines, and further including means for selectively diverting current flow from said current sources to a current sink during the application of said second voltage level to said word line to maintain the voltage on said bit lines at said selected voltage level.
Claim 10
Dependent Claim
130 words
A memory circuit comprising a word line, a pair of bit lines, a bipolar memory cell coupled between the bit lines means coupled to the word line for selectively setting the word line at first and second voltage levels, said second voltage level being at a magnitude lower than said first voltage level, and means for maintaining a selected voltage level on each of said bit lines including a pair of current sources each being coupled between a reference voltage and a respective one of said bit lines, and further including means for selectively diverting current flow from said current sources to a current sink during the application of said second voltage level to said word line to maintain the voltage on said bit lines at said selected voltage level.
Claim 11
Dependent Claim
40 words
The circuit of claim 8 wherein said means for selectively diverting current flow includes a standby reference circuit controlled by a clock coupled to an error reference circuit and to each of said bit lines through a respective semiconductor device.
Claim 12
Dependent Claim
66 words
The circuit of claim 8 wherein said means for selectively diverting current flow includes a standby reference circuit, an error reference circuit, a common output transistor, and a pair of semiconductor diodes, said standby reference circuit being coupled to said error reference circuit and through said common output transistor and a respective one of said diodes to a respective one of said pair of bit lines.
References Cited (Backward Citations)
US3909631A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-23 | 1982-04-24 | 1982-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-23 | 1986-04-24 | 1986-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-23 | 1990-04-24 | 1990-10-24 | $7700.00 | Window Closed / Lapsed |