Abstract This specification discloses an associative memory storage cell having two cross-connected transistors with the word line for the cell connected to the common emitters of the two transistors and having each of the bases of the two transistors connected to the base of an input/output transistor. This emitter of each of these input/output transistors is connected to a separate bit line and the collectors of the input/output transistors are connected together and to the associative sense amplifier. To associatively search the memory, one of the bit lines is lowered. This causes the input/output transistor connected to the lowered bit line to conduct and thereby give a no-match signal to the associative sense amplifier if its base is connected to the base of the conducting one of the two cross-connected transistors and it causes that transistor to remain nonconductive and thereby give a match signal to the associative sense amplifier if it is connected to the base of the nonconducting one of the two crossconnected transistors.
In a storage cell having a pair of transistors with bases and collectors cross connected, and emitters connected to a word line, and having input/output transistors each with a base coupled to the base of one of the cross-connected transistors and emitter connected to a different bit line of a bit line pair so that the data in the storage cell can alternatively be electrically coupled and decoupled from the bit lines, the improvement comprising the collectors of the two input/output transistors being connected together and to a common associative sense detector and means for raising and lowering the potential on the bit lines independently of one another so that the storage cell can be interrogated associatively by raising and lowering the potentials on the bit lines.
Claim 2
Dependent Claim
127 words
In a storage cell having a pair of transistors with bases and collectors cross connected, and emitters connected to a word line, and having input/output transistors each with a base coupled to the base of one of the cross-connected transistors and emitter connected to a different bit line of a bit line pair so that the data in the storage cell can alternatively be electrically coupled and decoupled from the bit lines, the improvement comprising the collectors of the two input/output transistors being connected together and to a common associative sense detector and means for raising and lowering the potential on the bit lines independently of one another so that the storage cell can be interrogated associatively by raising and lowering the potentials on the bit lines.
Claim 3
Dependent Claim
38 words
The storage cell of claim 1 including a load transistor for each of the cross-connected transistors each having its collector connected to the collector of a cross-connected transistor and an emitter connected to a source of driving potential.
Claim 4
Dependent Claim
24 words
The storage cell of claim 2 wherein said load transistors are of one conductivity type and the cross-connected transistors are of another conductivity type.
Claim 5
Dependent Claim
17 words
The structure of claim 3 wherein said load transistors are PNP-transistors and the cross-connected transistors are NPN-transistors.
Claim 6
Dependent Claim
17 words
The structure of claim 1 wherein the two cross-connected transistors are formed with a common emitter region.
Claim 7
Dependent Claim
27 words
The structure of claim 4 wherein the load transistors are lateral transistors with a common emitter region and separate collector regions formed in a common base region.