Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
88 words
An integrated circuit disposed on a substrate comprising: first circuit means being capable of storing a signal and including means for providing the signal state of said first circuit means during a sense mode; and second circuit means to generate a reference signal and being coupled to said first circuit means for supplying the reference signal during the sense mode, the reference signal providing an amplitude reference, said first and second circuit means each having an impedance means, each impedance means being substantially identical during said sense mode.
Claim 2
Dependent Claim
88 words
An integrated circuit disposed on a substrate comprising: first circuit means being capable of storing a signal and including means for providing the signal state of said first circuit means during a sense mode; and second circuit means to generate a reference signal and being coupled to said first circuit means for supplying the reference signal during the sense mode, the reference signal providing an amplitude reference, said first and second circuit means each having an impedance means, each impedance means being substantially identical during said sense mode.
Claim 3
Dependent Claim
33 words
An integrated circuit disposed on a substrate as in claim 1 further including: a. terminal means coupled to said first and second circuit means for supplying an enablng signal during the sense mode.
Claim 4
Dependent Claim
37 words
An integrated circuit disposed on a substrate as in claim 2 wherein: a. said first circuit means comprises a memory cell; and b. said second circuit means comprises a threshold voltage generating circuit for said memory cell.
Claim 5
Dependent Claim
37 words
An integrated circuit disposed on a substrate as in claim 3 wherein: a. said memory cell comprises a cross-coupled semiconductor memory cell, each half of said cross-coupled memory cell being symmetrical with respect to the other half.
Claim 6
Dependent Claim
95 words
An integrated circuit disposed on a substrate as in claim 4 wherein: a. said impedance means associated with said memory cell comprises a first output impedance means, constituting a portion of one half of said memory cell and a second output impedance means constituting a portion of the other half of said memory cell, and b. said impedance means associated with said threshold voltage generating source being disposed on substrate in close proximity to said memory cell, and c. said first output, second output and threshold voltage generating source impedance means being of equal value.
Claim 7
Dependent Claim
12 words
An integrated circuit disposed on a substrate as in claim 5 wherein:
Claim 8
Dependent Claim
23 words
a. said first output impedance means, said second output impedance means and said threshold voltage generating impedance means each comprise identical circuit elements.
Claim 9
Dependent Claim
23 words
a. said first output impedance means, said second output impedance means and said threshold voltage generating impedance means each comprise identical circuit elements.
Claim 10
Dependent Claim
25 words
An integrated circuit disposed on a substrate as in claim 6 wherein: a. said identical circuit elements comprise a transistor, a resistor and a diode.
Claim 11
Dependent Claim
88 words
A bipolar memory array having an on-chip voltage source, comprising: a plurality of memory cells arranged in an array; at least one means for generating a reference voltage; and at least a first and a second unity gain circuit for coupling the reference voltage from the at least one means to the array, the first and second unit gain circuits being coupled to selected memory cells, the at least one means having a portion exhibiting an impedance substantially equal to an impedance exhibited by a selected memory cell.
Claim 12
Dependent Claim
88 words
A bipolar memory array having an on-chip voltage source, comprising: a plurality of memory cells arranged in an array; at least one means for generating a reference voltage; and at least a first and a second unity gain circuit for coupling the reference voltage from the at least one means to the array, the first and second unit gain circuits being coupled to selected memory cells, the at least one means having a portion exhibiting an impedance substantially equal to an impedance exhibited by a selected memory cell.