Patent US1856147A successfully refreshed from Google Patents.
Patent US4291246A successfully refreshed from Google Patents.
US4291246A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Differential capacitive buffer
Assignee: Motorola Solutions Inc
•
Filing: 1979-03-05
•
Granted: 1981-09-22
•
Expires: 1999-03-05
Abstract
Abstract A balanced differential circuit is provided which is useful as an address buffer in digital memories. The circuit is illustrated as a single ended input circuit having complementary outputs. Capacitors are used to couple imbalancing signals into the circuit. Through selective timing of load devices within the circuit power dissipation is kept to a minimum.
Inventors
- 👤 William L. Martino, Jr.
- 👤 Jerry D. Moench
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:00
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356026
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
111 words
A buffer circuit useful in a digital memory and having a single ended input and providing complementary outputs, comprising: a first and a second cross-coupled field effect transistor; a first load device coupled to the first transistor; a second load device coupled to the second transistor; an input transistor coupled in parallel to the first transistor and having a control electrode for receiving the input; and a first and a second capacitor, the first capacitor being coupled to the second transistor for applying a first control signal to the second transistor, and the second capacitor being coupled to the first transistor for applying a second control signal to the first transistor.
Claim 2
Dependent Claim
111 words
A buffer circuit useful in a digital memory and having a single ended input and providing complementary outputs, comprising: a first and a second cross-coupled field effect transistor; a first load device coupled to the first transistor; a second load device coupled to the second transistor; an input transistor coupled in parallel to the first transistor and having a control electrode for receiving the input; and a first and a second capacitor, the first capacitor being coupled to the second transistor for applying a first control signal to the second transistor, and the second capacitor being coupled to the first transistor for applying a second control signal to the first transistor.
Claim 3
Dependent Claim
128 words
A buffer circuit useful in a digital memory and having a single ended input in providing complementary outputs, comprising: a first and a second cross-coupled field effect transistor; a first load device coupled to the first transistor; a second load device coupled to the second transistor; an input transistor coupled in parallel to the first transistor and having a control electrode for receiving the input; a first and a second capacitor, the first capacitor being coupled to the second transistor for applying a first control signal to the second transistor, and the second capacitor being coupled to the first transistor for applying a second control signal to the first transistor; and a third transistor in parallel with the second transistor to provide balanced symmetry of the buffer circuit.
Claim 4
Dependent Claim
128 words
A buffer circuit useful in a digital memory and having a single ended input in providing complementary outputs, comprising: a first and a second cross-coupled field effect transistor; a first load device coupled to the first transistor; a second load device coupled to the second transistor; an input transistor coupled in parallel to the first transistor and having a control electrode for receiving the input; a first and a second capacitor, the first capacitor being coupled to the second transistor for applying a first control signal to the second transistor, and the second capacitor being coupled to the first transistor for applying a second control signal to the first transistor; and a third transistor in parallel with the second transistor to provide balanced symmetry of the buffer circuit.
Claim 5
Dependent Claim
155 words
A buffer circuit useful in a digital memory and having a single ended input and providing complementary outputs, comprising: a first and a second cross-coupled field effect transistor; a first load device coupled to the first transistor; a second load device coupled to the second transistor; an input transistor coupled in parallel to the first transistor and having a control electrode for receiving the input. a first and a second capacitor, the first capacitor being coupled to the second transistor for applying a first control signal to the second transistor, and the second capacitor being coupled to the first transistor for applying a second control signal to the first transistor; and a first reset transistor in parallel with the input transistor and a second reset transistor in parallel with the second transistor, the first and second reset transistors being controllable by an enabling signal to enable the first and second transistors at a predetermined time.
Claim 6
Dependent Claim
155 words
A buffer circuit useful in a digital memory and having a single ended input and providing complementary outputs, comprising: a first and a second cross-coupled field effect transistor; a first load device coupled to the first transistor; a second load device coupled to the second transistor; an input transistor coupled in parallel to the first transistor and having a control electrode for receiving the input. a first and a second capacitor, the first capacitor being coupled to the second transistor for applying a first control signal to the second transistor, and the second capacitor being coupled to the first transistor for applying a second control signal to the first transistor; and a first reset transistor in parallel with the input transistor and a second reset transistor in parallel with the second transistor, the first and second reset transistors being controllable by an enabling signal to enable the first and second transistors at a predetermined time.
Claim 7
Dependent Claim
134 words
A buffer circuit useful in a digital memory having a single ended input and providing complementary outputs, comprising: a first and a second cross-coupled field effect transistor; a first load device coupled to the first transistor; a second load device coupled to the second transistor; an input transistor coupled in parallel to the first transistor and having a control electrode for receiving the input; a first and a second capacitor, the first capacitor being coupled to the second transistor for applying a first control signal to the second transistor, and the second capacitor being coupled to the first transistor for applying a second control signal to the first transistor; and wherein the first and second load devices are each a field effect transistor each having a control electrode commonly coupled to a timing signal.
Claim 8
Dependent Claim
134 words
A buffer circuit useful in a digital memory having a single ended input and providing complementary outputs, comprising: a first and a second cross-coupled field effect transistor; a first load device coupled to the first transistor; a second load device coupled to the second transistor; an input transistor coupled in parallel to the first transistor and having a control electrode for receiving the input; a first and a second capacitor, the first capacitor being coupled to the second transistor for applying a first control signal to the second transistor, and the second capacitor being coupled to the first transistor for applying a second control signal to the first transistor; and wherein the first and second load devices are each a field effect transistor each having a control electrode commonly coupled to a timing signal.
Claim 9
Dependent Claim
99 words
An electronic circuit having a balanced flip-flop with controllable load devices and having an input, a first and a second output, and first and second voltage terminals, comprising: an input field effect transistor coupled to the input, a balancing field effect transistor coupled to the second output and having a first current carrying electrode and a control electrode coupled to the second voltage terminal; a first capacitor coupled to the first output for coupling a first unbalancing signal into the flip-flop; and a second capacitor coupled to the second output for coupling a second unbalancing signal into the flip-flop.
Claim 10
Dependent Claim
99 words
An electronic circuit having a balanced flip-flop with controllable load devices and having an input, a first and a second output, and first and second voltage terminals, comprising: an input field effect transistor coupled to the input, a balancing field effect transistor coupled to the second output and having a first current carrying electrode and a control electrode coupled to the second voltage terminal; a first capacitor coupled to the first output for coupling a first unbalancing signal into the flip-flop; and a second capacitor coupled to the second output for coupling a second unbalancing signal into the flip-flop.
Claim 11
Dependent Claim
48 words
The electronic circuit of claim 5 having a first field effect transistor coupled to the first output for precharging the first output to a predetermined voltage level, and a second field effect transistor coupled to the second output for precharging the second output to the predetermined voltage level.
Claim 12
Dependent Claim
18 words
The electronic circuit of claim 5 wherein the first and second unbalancing signals are complements of each other.
Claim 13
Dependent Claim
128 words
A buffer circuit comprising: a first field effect transistor having a source, drain, and control electrode; a second field effect transistor having a source, drain and control electrode; which has its control electrode coupled to the drain of the first field effect transistor, its drain coupled to the control electrode of the first field effect transistor, and its source coupled to the source of the first field transistor; a first load device coupled to the first transistor; a second load device coupled to the second transistor; an input transistor coupled in parallel to the first transistor and having a control electrode for receiving an input signal; capacitance means for capacitively coupling an unbalancing signal to the control electrode of at least one of the first and second transistors.
Claim 14
Dependent Claim
128 words
A buffer circuit comprising: a first field effect transistor having a source, drain, and control electrode; a second field effect transistor having a source, drain and control electrode; which has its control electrode coupled to the drain of the first field effect transistor, its drain coupled to the control electrode of the first field effect transistor, and its source coupled to the source of the first field transistor; a first load device coupled to the first transistor; a second load device coupled to the second transistor; an input transistor coupled in parallel to the first transistor and having a control electrode for receiving an input signal; capacitance means for capacitively coupling an unbalancing signal to the control electrode of at least one of the first and second transistors.
Claim 15
Dependent Claim
63 words
The buffer circuit of claim 8 further comprising: a first reset means coupled to a control electrode of the second transistor for resetting the control electrode of the second transistor to a predetermined voltage level; and a second reset means coupled to a control electrode of the first transistor for resetting the control electrode of the first transistor to the predetermined voltage level.
Claim 16
Dependent Claim
35 words
The buffer circuit of claim 9 further comprising a third transistor coupled in parallel to the second transistor with a control electrode of the third transistor biased to provide balanced symmetry to the input transistor.
References Cited (Backward Citations)
US3987315A
Cited
US4031415A
Cited
US4023050A
Cited
US4077031A
Cited
US4149099A
Cited
US4110842A
Cited
US4110639A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-21 | 1985-03-23 | 1985-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-21 | 1989-03-23 | 1989-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-21 | 1993-03-23 | 1993-09-22 | $7700.00 | Window Closed / Lapsed |