Amplifier circuit for obtaining true and complementary output signals from an input signal

Claim 2

A transistor circuit comprising first and second nodes, a pair of cross-coupled transistors connected to said first and second nodes, means for operatively charging said first and second nodes with a first level, input means, including an input terminal, for determining the potential of said first node in accordance with an input signal applied to said input terminal, capacitance means, and switching means, arranged between said capacitance means and said second node for partially transferring electric charge stored in said second node at said first level into said capacitance means to change the potential of said second node to a second level lower than said first level in absolute value.

Claim 3

The transistor circuit of claim 1, further comprising means for deriving a first output signal and a second output signal from said first and second nodes, said second output signal being complementary in logic level with respect to said first output signal.

Claim 4

An amplifier circuit comprising first and second nodes, a pair of insulated-gate type field-effect transistors cross-coupled with each other and connected to said first and second nodes, first means coupled with said first and second nodes for adjusting potentials of said first and second nodes to a first level in a first time period, a capacitor, second means for coupling said second node to said capacitor to change, in a second time period the potential of said second node from said first level to a second level lower than said first level in absolute value, third means, coupled with said first node, and responsive to an input signal, for determing the potential of said first node to be either said first level or a third level which is lower than said second level in absolute value, and output means coupled with said first and second nodes for deriving a first output signal and a second output signal, said second output signal being complementary in logic level to said first output signal.

Claim 5

An amplifier circuit comprising first and second nodes, a pair of insulated-gate type field-effect transistors cross-coupled with each other and connected to said first and second nodes, first means coupled with said first and second nodes for adjusting potentials of said first and second nodes to a first level in a first time period, a capacitor, second means for coupling said second node to said capacitor to change, in a second time period the potential of said second node from said first level to a second level lower than said first level in absolute value, third means, coupled with said first node, and responsive to an input signal, for determing the potential of said first node to be either said first level or a third level which is lower than said second level in absolute value, and output means coupled with said first and second nodes for deriving a first output signal and a second output signal, said second output signal being complementary in logic level to said first output signal.

Claim 6

The amplifier circuit of claim 3, further comprising fourth means for activating the cross-coupled transistors in a third time period.

Claim 7

The amplifier circuit of claim 3, in which said second means includes a first switch connected between said second node and said capacitor, wherein said first switch sends a part of the charge at said second node to said capacitor in said second time period to lower the potential level of said second node to said second level.

Claim 8

The amplifier circuit of claim 5, in which said second means further includes means for discharging said capacitor before said second time period.

Claim 9

The amplifier circuit of claim 5, in which said first switch includes an insulated-gate type field-effect transistor connected between said second node and said capacitor, a gate of which is supplied with a timing signal for said second time period.

Claim 10

The amplifier circuit of claim 5, in which said third means includes a second switch for discharging charge at said first node in response to a predetermined state of said input signal to lower the potential level of said first node to said third level.

Claim 11

The amplifier circuit of claim 8, in which said second switch includes an insulated-gate type field-effect transistor connected through a d.c. current path between said first node and a common potential, a gate of which is supplied with said input signal.

Claim 12

The amplifier circuit of claim 8, in which said first means includes third and fourth switches connected respectively to said first and second nodes for charging said first and second nodes with a power supply in said first time period and a fifth switch connected between said first and second nodes for unifying potential levels of said first and second nodes in said first time period.

Claim 13

The amplifier circuit of claim 10, in which said output means includes a buffer circuit.

Claim 14

A semi-conductor circuit using insulated-gate type field-effect transistors comprising: a pair of insulated-gate type transistors whose sources are commonly connected and whose drains and gates are cross-connected; first switch means for connecting a common junction of said sources to a reference potential; first and second capacitors connected to respective drains of said pair of transistors; means for precharging said first and second capacitors to an equal potential; second switch means for discharging the precharged charges in said first capacitor dependent on and in response to a control input signal a third capacitor; and third switch means for dividing and allotting the pre-charged charges in said second capacitor to said third capacitor.

Claim 15

A semi-conductor circuit using insulated-gate type field-effect transistors comprising: a pair of insulated-gate type transistors whose sources are commonly connected and whose drains and gates are cross-connected; first switch means for connecting a common junction of said sources to a reference potential; first and second capacitors connected to respective drains of said pair of transistors; means for precharging said first and second capacitors to an equal potential; second switch means for discharging the precharged charges in said first capacitor dependent on and in response to a control input signal a third capacitor; and third switch means for dividing and allotting the pre-charged charges in said second capacitor to said third capacitor.