CMOS Memory sense amplifier

Claim 1

A sense amplifier connected to an array of memory cells by means of a pair of data bus lines so as to sense information signals contained in selected ones of the memory cells, said sense amplifier comprising: first and second pairs of multi-terminal transistor devices having respective conduction paths and control electrodes, first transistor devices from each of said first and second pairs thereof connected in electrical series with one another between first and second electrical junctions, second transistor devices from each of said first and second pairs thereof connected in electrical series with one another between third and fourth electrical junctions, the control electrode of the first transistor device of said first pair thereof connected to a conduction path electrode of the second transistor device of said first pair thereof, and the control electrode of the second transistor device of said first pair thereof connected to a conduction path electrode of said first transistor device of said first pair thereof, each of the respective control electrodes of the transistor devices of said second pair thereof connected to a corresponding data bus line, whereby a relatively high input impedance is achieved for said sense amplifier, each of the multi-terminal transistor devices of the first pair thereof being a p-channel field effect transistor, each of the multi-terminal transistor devices of the second pair thereof being a n-channel field effect transistor, said first and third electrical junctions being common electrical junctions, said second and fourth electrical junctions being common electrical junctions, a source of recurring strobe input signals to control the conductivity of said sense amplifier, a first source of supply voltage, a first additional multi-terminal transistor device having a conduction path and a control electrode, the control electrode of said first additional transistor device connected to said source of strobe signals, and the conduction path of said first additional transistor device selectively connecting each of the second and fourth electrical junctions to said first source of supply voltage to thereby enable said sense amplifier, a second source of supply voltage wherein the first and third electrical junctions are connected to said second source of supply voltage, a second additional multi-terminal transistor device having a conduction path and a control electrode, the control electrode of said second additional transistor device connected to said source of strobe signals, and the conduction path of said second additional transistor device connected between the connection of the control electrode of the first transistor device of said first pair thereof to the conduction path electrode of the second transistor device of said first pair thereof and the connection of the control electrode of the second transistor device of said first pair thereof to the conduction path electrode of the first transistor device of said first pair thereof, said first and second additional multi-terminal transistor devices being field effect transistors having an opposite conductivity type relative to one another, the interconnection of said first and second pairs of multi-terminal transistor devices forms a data latch, the control electrodes of each of said second pair of transistor devices corresponding to data latch input terminals, the connection of the control electrode of the first transistor device of said first pair thereof to the conduction path electrode of the second transistor device of said first pair thereof and the connection of the control electrode of the second transistor device of said first pair thereof to the conduction path electrode of the first transistor device of said first pair thereof corresponding to data latch output terminals, first and second amplifier stages, each of said stages having input and output terminals, the data latch output terminals respectively connected to the input terminals of said first and second amplifier stages, each of said first and second amplifier stages being comprised of a pair of series connected field effect transistors having an opposite conductivity type relative to one another, and said data bus lines being precharged to reduce amplifier access time to data stored in said cells and to preserve said data in a radiation environment.