Dynamic random access memory having sense amplifier circuits and data regeneration circuit for increased speed

Claim 1

A dynamic Random Access Memory comprising: a sense amplifier circuit consisting of a flip-flop circuit having two nodes and a ground terminal, and a voltage setting circuit for setting the voltage at the ground terminal of the flip-flop circuit; two data lines each respectively connected to one of two nodes of the flip-flop circuit; a first memory cell array connected to one of the data lines and having a plurality of memory cells; a second memory cell array connected to the other data line and having the same number of memory cells as the first memory cell array; two dummy cells each respectively conected between the sense amplifier circuit and one of the first and second memory cell arrays, for writing an intermediate potential between the "1" and "0" states into the two nodes of the flip-flop circuit, whereby when data is being read out, the two data lines are charged to the "1" state, and minute voltage changes read out into the data lines from a selected memory cell and a dummy cell are sensed by the flip-flop circuit, after which the voltage at the ground terminal of the flip-flop circuit is gradually discharged to the "0" state, a "1" voltage regeneration circuit connected to one of the data lines and consisting of first and second transistors having source, gate and drain electrodes, and first and second capacitors respectively connected between the gate electrodes and source electrodes of the transistors, the source electrode of the first transistor being connected with the gate electrode of the second transistor, the gate electrode of the first transistor and the source electrode of the second transistor being commonly connected with one of the data lines, and input terminals for supplying various clock pulses to the drain electrodes of the first and second transistors.