Memory accessing system

Claim 2

A memory accessing system comprising a plurality of word drive lines, means for applying a drive pulse to one end of said drive lines, a decode circuit having a plurality of outputs coupled to the one end of said drive lines for controlling the application of said drive pulse to said drive lines, and a pull-down circuit having a plurality of latches connected to the other end of said drive lines and responsive to said drive pulse to set said latches in a first state and means for applying a restore pulse at predetermined periodic intervals to said latches to set said latches in a second state.

Claim 3

A memory system comprising a word line having a normally capacitive impedance, a plurality of bit/sense lines, a plurality of memory cells each coupled to said word line at spaced apart points and to one of said bit/sense lines for applying signals to said cells during data time intervals, a first circuit including means for producing drive pulses during said data time intervals coupled to one end of said word line, and a second circuit coupled to the other end of said word line and having first and second states, said first state being a low resistive impedance state and said second state being a high capacitive impedance state, said second circuit including a restore circuit and means for applying pulses to said restore circuit at predetermined periodic intervals outside of said data time intervals to establish said second circuit in said first state, and said second circuit being responsive to said drive pulses for switching said second circuit to said high capacitive impedance state.

Claim 4

A memory system comprising a word line having a normally capacitive impedance, a plurality of bit/sense lines, a plurality of memory cells each coupled to said word line at spaced apart points and to one of said bit/sense lines for applying signals to said cells during data time intervals, a first circuit including means for producing drive pulses during said data time intervals coupled to one end of said word line, and a second circuit coupled to the other end of said word line and having first and second states, said first state being a low resistive impedance state and said second state being a high capacitive impedance state, said second circuit including a restore circuit and means for applying pulses to said restore circuit at predetermined periodic intervals outside of said data time intervals to establish said second circuit in said first state, and said second circuit being responsive to said drive pulses for switching said second circuit to said high capacitive impedance state.

Claim 5

A memory system as set forth in claim 2 wherein one of said predetermined periodic intervals precedes each of said data time intervals and said second circuit in said first state connects said word line to ground during said predetermined periodic intervals.

Claim 6

A meMory system as set forth in claim 3 wherein each of said memory cells includes a field effect transistor having a gate electrode coupled to said word time and a current carrying electrode coupled to one of said bit/sense lines.

Claim 7

A memory system comprising a plurality of memory cells, a memory line coupled to each of said cells at spaced apart points normally forming a capacitive impedance with said cells, a first circuit including means for producing drive pulses coupled to one end of said memory line, and a second circuit coupled to the other end of said line and having first and second states, said first state being a low resistive impedance state and said second state being a high capacitive impedance state, said second circuit including a restore circuit and means for applying pulses to said restore circuit at predetermined periodic intervals to establish said second circuit in said first state, and said second circuit being responsive to said drive pulses for switching said second circuit to said high capacitive impedance state.

Claim 8

A memory system comprising a plurality of memory cells, a memory line coupled to each of said cells at spaced apart points normally forming a capacitive impedance with said cells, a first circuit including means for producing drive pulses coupled to one end of said memory line, and a second circuit coupled to the other end of said line and having first and second states, said first state being a low resistive impedance state and said second state being a high capacitive impedance state, said second circuit including a restore circuit and means for applying pulses to said restore circuit at predetermined periodic intervals to establish said second circuit in said first state, and said second circuit being responsive to said drive pulses for switching said second circuit to said high capacitive impedance state.

Claim 9

A memory system as set forth in claim 5 wherein each of said cells includes a field effect transistor having a gate electrode coupled to said memory line.

Claim 10

A memory system as set forth in claim 5 wherein said first circuit includes a decode circuit and said second circuit includes a pull-down circuit.

Claim 11

A memory accessing system as set forth in claim 7 wherein said pull-down circuit is a latch.

Claim 12

A memory system as set forth in claim 5 wherein said second circuit in said first state connects said memory line to a point of reference potential.

Claim 13

A memory system as set forth in claim 9 wherein said point of reference potential is ground.

Claim 14

A memory accessing system comprising a semiconductor chip, a plurality of memory cells aligned in said chip and having a given pitch, a drive line interconnecting said plurality of cells, a decode circuit and means for applying a drive pulse coupled to one end of said drive line and formed within said chip in alignment with said plurality of cells within said given pitch, and a pull-down circuit coupled to the other end of said drive line, responsive to said drive pulse and formed within said chip in alignment with said cells and within said given pitch to establish said pull-down circuit in a first state and means for applying a restore pulse at predetermined periodic intervals to said pull-down circuit to switch said pull-down circuit to a second state.

Claim 15

A memory accessing system comprising a semiconductor chip, a plurality of memory cells aligned in said chip and having a given pitch, a drive line interconnecting said plurality of cells, a decode circuit and means for applying a drive pulse coupled to one end of said drive line and formed within said chip in alignment with said plurality of cells within said given pitch, and a pull-down circuit coupled to the other end of said drive line, responsive to said drive pulse and formed within said chip in alignment with said cells and within said given pitch to establish said pull-down circuit in a first state and means for applying a restore pulse at predetermined periodic intervals to said pull-down circuit to switch said pull-down circuit to a second state.

Claim 16

A memory accessing system as set forth in claim 11 wherein said drive line is a word line and said pull-down circuit includes a latch responsive to said drive pulse to set said latch in the first state.

Claim 17

A memory accessing system as set forth in claim 12 wherein said cells each include a capacitor and a field effect transistor having a gate connected to said word line and said latch includes first and second field effect transistors, the gate of said first transistor being connected to the other end of said word line and the gate of said second transistor being connected to said restore pulse applying means.

Claim 18

A memory accessing system as set forth in claim 13 wherein said means for applying a drive pulse to said word line includes a transistor having a gate connected to said decode circuit.

Claim 19

A memory accessing system comprising a plurality of memory cells each including a capacitor and a field effect transistor having a gate coupled to a word drive line, a decode circuit coupled to one end of said drive line and means for applying a drive pulse to said one end of said word line, and a pull-down circuit connected to the other end of said word line, said pull-down circuit including a latch responsive to said drive pulse to set said latch in a first state, and means for applying a restore pulse at predetermined periodic intervals to said latch to set said latch in a second state.

Claim 20

A memory accessing system comprising a plurality of memory cells each including a capacitor and a field effect transistor having a gate coupled to a word drive line, a decode circuit coupled to one end of said drive line and means for applying a drive pulse to said one end of said word line, and a pull-down circuit connected to the other end of said word line, said pull-down circuit including a latch responsive to said drive pulse to set said latch in a first state, and means for applying a restore pulse at predetermined periodic intervals to said latch to set said latch in a second state.

Claim 21

A memory accessing system as set forth in claim 15 wherein said latch includes first and second field effect transistors, the gate of said first transistor being connected to the other end of said word line and the gate of said second transistor being connected to said restore pulse applying means.