Functional storage array

Claim 2

An associative array of four-state cells, each having a pair of bistable latches comprises of insulated gate field effect transistors, the cells being arranged in a plurality of words each having a plurality of cell positions, means operating the array in at least write and search/select modes, a write enable line for each word, each line being adapted to receive write signals during the write mode of operation, a word line for each word, only one pair of data lines for corresponding cell positions of the words, means providing input data signals and search argument signals for each pair of date lines, a driver circuit for each pair of data lines and including insulated gate field effect transistor means responsive to respective input data signals for concurrently applying selected binary input signals to the respective pair of data lines and responsive to respective search argument signals for concurrently applying selected binary search signals to the respective pair of data lines, first and second insulated gate field effect transistors in each cell responsive to a write signal on a respective write enable line for coupling each one of a respective pair of data lines to a respective latch in the cell to set the latches to logical states according to the binary input signals on the data lines, third and fourth insulated gate field effect transistors in each cell, each selectively coupling one of a respective pair of data lines to A respective word line according to the state of a respective one of the cell latches, and a selector latch means coupled to each word line and set to one or the other of its states during search/select cycles as a function of the presence or absence of predetermined relationships between the binary search signals on the data lines and the logical states of the cell latches of the respective word.

Claim 3

The array set forth in claim 1 wherein each driver circuit comprises a first input line for receiving a binary data portion of said input data signals, a second input line for receiving a don''t care portion of said input data signals, a pair of junctions, field effect transistor means connected to the first and second lines and responsive to the logical value of the data portion concurrent with the presence of the don''t care portion for applying the same selected data signal value to both junctions, field effect transistor means connected to the first and second lines and responsive to the logical value of the data portion concurrent with the absence of the don''t care portion for applying complementary data signal values selectively to the junctions, and field effect transistor means selectively operated during search/select and write cycles for coupling the junctions to respective ones of the respective pair of data lines.

Claim 4

The array set forth in claim 1 wherein each latch comprises first and second pairs of series-connected insulated gate field effect transistors cross-coupled to provide a latching function.

Claim 5

The array set forth in claim 2 wherein each latch comprises first and second pairs of series-connected insulated gate field effect transistors cross-coupled to provide a latching function.

Claim 6

The array set forth in claim 4 wherein the driver field effect transistor means and the latch transistors are complementary transistors operated in the enhancement mode for minimizing power drain.

Claim 7

The array set forth in claim 4 further comprising a power supply having only two terminals at different potential levels for supplying all power for the array and its cells and driver circuits, said binary data portion and said don''t care portion of said input signals each having two alternative logical levels essentially equal to one and the other of said potential levels.

Claim 8

An associative array of the type wherein four-state cells, each having a pair of bistable latches, are arranged in a plurality of multiple-bit words, wherein a plurality of write enable lines are provided, each coupled to all cells of a respective word, said lines being adapted to receive write signals for initiating the writing of data into the coupled cells during write cycles, wherein a plurality of word lines are provided, each coupled to all cells of a respective word, said word lines being adapted to receive read signals for initiating the reading of data from certain of the coupled cells during read cycles and being adapted to selectively receive mismatch signals from others of the coupled cells during search/select cycles, wherein means, including respective selector latch connected to each word line, responds to the absence of mismatch signal during search/select cycles to identify matches between input search data and data stored in certain cells in the respective word, and wherein means are provided for operating the array to store pairs of binary signals concurrently into selected data cells, to read pairs of binary signals concurrently out of the data cells, and to apply mismatch signals concurrently to the word lines during write, read and search/select cycles respectively, the array further comprising only one pair of data lines being provided for each bit position of the words in the array, a cell driver circuit for each pair of data lines, each circuit including insulated gate field effect transistor means selectively operated to couple selected binary data signals to its pAir of data lines during search/select and write cycles, first and second insulated gate field effect transistors in each cell for each pair of data lines, each transistor having a gate electrode connected to the respective write enable line and responsive to write signals for coupling a respective one of the pair of data lines to a respective one of the cell latches, third and fourth insulated gate field effect transistors in each cell for each pair of data lines, each latter transistor having a gate electrode connected to a respective one of the cell latches and responsive to a selected logical state of the latch for coupling a respective one of its pair of data lines to its respective word line, thereby to selectively apply signals on the respective data line to the respective word line as mismatch signals during search/select cycles, and to selectively apply read signals on the respective word line to the respective data line during read cycles, and a sense amplifier for each pair of data lines, each amplifier selectively operated to sense said read signals on its pair of data lines during read cycles.

Claim 9

An associative array of the type wherein four-state cells, each having a pair of bistable latches, are arranged in a plurality of multiple-bit words, wherein a plurality of write enable lines are provided, each coupled to all cells of a respective word, said lines being adapted to receive write signals for initiating the writing of data into the coupled cells during write cycles, wherein a plurality of word lines are provided, each coupled to all cells of a respective word, said word lines being adapted to receive read signals for initiating the reading of data from certain of the coupled cells during read cycles and being adapted to selectively receive mismatch signals from others of the coupled cells during search/select cycles, wherein means, including respective selector latch connected to each word line, responds to the absence of mismatch signal during search/select cycles to identify matches between input search data and data stored in certain cells in the respective word, and wherein means are provided for operating the array to store pairs of binary signals concurrently into selected data cells, to read pairs of binary signals concurrently out of the data cells, and to apply mismatch signals concurrently to the word lines during write, read and search/select cycles respectively, the array further comprising only one pair of data lines being provided for each bit position of the words in the array, a cell driver circuit for each pair of data lines, each circuit including insulated gate field effect transistor means selectively operated to couple selected binary data signals to its pAir of data lines during search/select and write cycles, first and second insulated gate field effect transistors in each cell for each pair of data lines, each transistor having a gate electrode connected to the respective write enable line and responsive to write signals for coupling a respective one of the pair of data lines to a respective one of the cell latches, third and fourth insulated gate field effect transistors in each cell for each pair of data lines, each latter transistor having a gate electrode connected to a respective one of the cell latches and responsive to a selected logical state of the latch for coupling a respective one of its pair of data lines to its respective word line, thereby to selectively apply signals on the respective data line to the respective word line as mismatch signals during search/select cycles, and to selectively apply read signals on the respective word line to the respective data line during read cycles, and a sense amplifier for each pair of data lines, each amplifier selectively operated to sense said read signals on its pair of data lines during read cycles.