MOS on-chip voltage sense amplifier circuit

Claim 2

An integrated MOS voltage sense amplifier circuit having the property of switching an output between high and low states in response to the relation between an input voltage and a reference voltage, said circuit comprising: comparator amplifier means having two voltage responsive input terminals and a single output terminal, the voltage level at said output terminal being a function of the difference in voltage levels at said input terminals and MOS process variables; buffer amplifier means having an input terminal coupled to said comparator amplifier means output terminal and an output terminal defining said output of said circuit; and compensating amplifier means having an input coupled to said comparator amplifier means output terminal and an output coupled to a node in said buffer amplifier means, said compensating amplifier means having an output conduction proportional to its input voltage whereby said circuit output switches as a function of the difference in voltage levels at said input terminals of said comparator amplifier means independent of said process variables.

Claim 3

The circuit of claim 1 wherein said comparator amplifier means comprise: first and second MOS transistors having their source-drain circuits coupled in series across a source of operating potential, the gate of said first transistor being coupled to the voltage sense input terminal and the jucture of said source drain circuits constituting said sense amplifier means output terminal; and third and fourth MOS transistors having their source-drain circuits coupled in series across said source of operating potential, the gate of said third transistor being coupled to said reference voltage, the juncture of said source-drain circuits being coupled to the gate of said second transistor, and the gate of said second transistor being coupled to said juncture of said first and second transistor source-drain circuits.

Claim 4

The circuit of claim 2 wherein said first, second, third, and fourth MOS transistors are all the same size.

Claim 5

The circuit of claim 2 wherein said buffer amplifier and said compensating amplifier means means comprise: fifth and sixth MOS transistors having their source-drain circuits coupled in series across a source of operating potential, the juncture of said source-drain circuits constituting a node representing said output of said circuit, and the gate of said fifth transistor being coupled to its drain whereby said fifth transistor acts as a load element for said sixth transistor: seventh and eighth MOS transistors having their source-drain circuits coupled in series across said source of operating potential, the juncture of said source-drain circuits being coupled to the gate of said sixth transistor, the gate of said seventh transistor being coupled to its drain whereby said seventh transistor being coupled to its drain whereby said seventh transistor acts as a load element for said eighth transistor, and the gate of said eighth transistor being coupled to said output terminal of said comparator amplifier means; ninth and tenth MOS transistors having their source-drain circuits coupled in series across said source of operating potential, and their gates coupled together and to said output terminal of said comparator amplifier means; and an eleventh MOS transistor having its source drain circuit coupled in parallel with the source-drain circuit of said eighth transistor and its gate coupled to the juncture of said source-drain circuits of said ninth and tenth transistors.

Claim 6

The circuit of claim 3 wherein a pair of resistors is coupled in series across said source of operating potential, the juncture of said resistors being coupled to said gate of said third transistor whereby said circuit senses a voltage that is a fraction of that of said source of operating potential independent of said process, said fraction being set by the values of said resistors.