High-density memory with non-volatile storage array

Claim 2

A composite memory array for storing binary words in a volatile state in response to control signals on complementary bit lines and word lines and for selectively storing binary words in a non-volatile state in response to control signals on row lines, said composite memory array comprising: a pair of access transistors that are respectively connected to the complementary bit lines and that are connected to a word line; a flip-flop circuit connected to the access transistors for storing binary data signals from the complementary bit lines in a volatile state in response to control signals provided to the word lines; and an array of non-volatile memory cells connected to the flip-flot circuit and to a plurality of row lines, said non-volatile array storing binary data signals from the flip-flop circuit at a selected non-volatile memory level in response to control signals selectively provided to the row lines.

Claim 3

The composite memory array of claim 1 wherein the non-volatile memory cells of said array include pairs of non-volatile devices that store complementary binary data from the flip-flop circuit.

Claim 4

The composite memory array of claim 2 wherein the non-volatile memory devices are comprised of metal-nitride-oxide-silicon transistors.

Claim 5

A composite memory array for storing binary words in a volatile state in response to control signals on complementary bit lines and on word lines and for selectively storing binary words in a non-volatile state in response to control signals on row lines, said composite memory array comprising: a pair of access transistors that are respectively connected to the complementary bit lines and that are connected to a word line; a flip-flop transistor pair connected to the access transistors, said flip-flop transistor pair providing gate voltages for storing binary data signals from the complementary bit lines in a volatile state in response to control signals provided to the word lines; an array of memory-type transistor pairs, the gates of each memory-type transistor pair being connected to a selected row line and one of the source or drain of each memory-type transistor being connected to a gate of the flip-flop transistor pair, said array of memory-type transistor pairs storing gate voltages of the flip-flop transistors in a selected memory-type transistor pair in response to control signals selectively provided to the row lines.

Claim 6

A composite memory array for storing binary words in a volatile state in response to control signals on complementary bit lines and on word lines and for selectively storing binary words in a non-volatile state in response to control signals on row lines, said composite memory array comprising: a pair of access transistors that are respectively connected to the complementary bit lines and that are connected to a word line; a flip-flop transistor pair connected to the access transistors, said flip-flop transistor pair providing gate voltages for storing binary data signals from the complementary bit lines in a volatile state in response to control signals provided to the word lines; an array of memory-type transistor pairs, the gates of each memory-type transistor pair being connected to a selected row line and one of the source or drain of each memory-type transistor being connected to a gate of the flip-flop transistor pair, said array of memory-type transistor pairs storing gate voltages of the flip-flop transistors in a selected memory-type transistor pair in response to control signals selectively provided to the row lines.

Claim 7

The composite memory array of claim 4 further comprising: a transfer structure for selectively connecting the flip-flop transistor pair to the array of memory-type transistors such that the flip-flop transistors can be disconnected from the array when erasing the memory-type transistors.

Claim 8

The composite memory array of claim 5 further comprising: means for erasing the data stored in a selected memory-type transistor pair of the non-volatile memory array by providing a voltage signal to said transistor pair having the same polarity as the control signal provided on the respective row line.

Claim 9

The composite memory array of claim 4 wherein the source region of each transistor pair is connected to a gate of the flip-flop transistor pair such that the memory-type transistor pairs store the gate voltages of the flip-flop transistor pair in accordance with the threshold voltage of the respective memory-type transistors.

Claim 10

The composite memory array of claim 7 wherein said array of memory-type transistor pairs is comprised of metal-nitride-oxide-silicon transistor pairs.