US3683335A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile memory element and array
Assignee: Westinghouse Electric Corp
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Filing: 1970-06-24
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Granted: 1972-08-08
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Expires: 1990-06-24
Abstract
Abstract A metal insulated semiconductor (MIS) field effect transistor is operated in a gate-to-source mode. The voltage threshold of conduction of the transistor is variable and is switched between two different stable threshold conditions in response to application of corresponding, different predetermined values of polarizing voltages applied between the gate and source terminals. Determination of the threshold condition to which the transistor is switched is effected by applying a read voltage to the gate of the transistor intermediate the voltage threshold levels and sensing the current flow between the source and drain. Since the sense voltage is less than the polarizing voltage for either condition of switching, the preset threshold condition is maintained. The transistor therefore exhibits a non-volatile memory capability. A plurality of the transistors are employed in a memory array and may be readily fabricated in integrated circuit form.
Inventors
- 👤 James R Cricchi
- 👤 William W Beydler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:44
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
129 words
A non-volatile memory system comprising: an array of field effect transistors each having gate, source, and drain electrodes and each having a voltage threshold for conduction variable between first and second stable threshold conditions, clear means for applying a first polarizing potential between the gate and source electrodes of a selected transistor of the array to cause the clear selected transistor to assume a first stable threshold condition, write means for applying a second polarizing potential between the gate and source electrodes of a selected transistor of the array to cause the clear selected transistor to assume a second stable threshold condition, and sense means for applying a read potential to a selected transistor of the array to detect the existing voltage threshold condition of the sense selected transistor.
Claim 2
Dependent Claim
129 words
A non-volatile memory system comprising: an array of field effect transistors each having gate, source, and drain electrodes and each having a voltage threshold for conduction variable between first and second stable threshold conditions, clear means for applying a first polarizing potential between the gate and source electrodes of a selected transistor of the array to cause the clear selected transistor to assume a first stable threshold condition, write means for applying a second polarizing potential between the gate and source electrodes of a selected transistor of the array to cause the clear selected transistor to assume a second stable threshold condition, and sense means for applying a read potential to a selected transistor of the array to detect the existing voltage threshold condition of the sense selected transistor.
Claim 3
Dependent Claim
72 words
A non-volatile memory system as recited in claim 1 wherein: said clear means applies a positive polarizing potential as the first polarizing potential to render the gate electrode of a clear selected transistor positive with respect to its associated source electrode, and said write means applies a negative voltage as the second polarizing potential to render the gate electrode of a write selected transistor negative with respect to the associated source electrode.
Claim 4
Dependent Claim
61 words
A non-volatile memory system as recited in claim 1 wherein said sense means includes: means for selectively applying a read voltage of less magnitude than either of said first and second polarizing potentials to the gate electrode of the transistor selected for sensing, and means for detecting current flow in the source to drain conduction path of a sense selected transistor.
Claim 5
Dependent Claim
152 words
A non-volatile memory system as recited in claim 1 wherein the transistors of said array are arranged in rows and columns and wherein there is further provided: a first group of access lines connected in common to the gate electrodes of the transistors oF respectively corresponding rows, and a second group of access lines connected in common to the source electrodes of the transistors of respectively corresponding columns, a third group of access lines connected in common to the drain electrodes of the transistors in the respectively corresponding rows, each of said clear and write means is selectively connected in time coincidence to one each of said first and second group of access lines for applying said first and second polarizing potentials, respectively, to the corresponding selected transistors, and said sense means is connected to said second group of access lines for detecting the voltage threshold conditions of a sense selected transistor.
Claim 6
Dependent Claim
30 words
A non-volatile memory system as recited in claim 4 wherein said third group of access lines are connected in common to a power supply terminal for energization of said transistors.
Claim 7
Dependent Claim
48 words
A non-volatile memory system as recited in claim 4 wherein there is further provided means for selectively energizing each of said third group of access lines in time coincidence with the corresponding one of said first group of access lines in energizing a selected transistor of said array.
Claim 8
Dependent Claim
55 words
A non-volatile memory system as recited in claim 4 wherein said clear means includes means for defining the access lines of said first and second groups thereof associated with a clear selected transistor for applying the first polarizing potential through the lines thus defined between the gate and the source of a clear selected transistor.
Claim 9
Dependent Claim
55 words
A non-volatile memory system as recited in claim 4 wherein said write means includes means for defining the access lines of said first and second groups thereof associated with a clear selected transistor for applying the first polarizing potential through the lines thus defined between the gate and the source of a write selected transistor.
References Cited (Backward Citations)
US3549911A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-08 | 1976-02-07 | 1976-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-08 | 1980-02-07 | 1980-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-08 | 1984-02-07 | 1984-08-08 | $7700.00 | Window Closed / Lapsed |