US4070655A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Virtually nonvolatile static random access memory device
Assignee: United States Department of the Air Force
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Filing: 1976-11-05
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Granted: 1978-01-24
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Expires: 1996-11-05
Abstract
Abstract A high density, static, virtually nonvolatile, Random Access Memory (RAM) cell is disclosed in which variable threshold n-channel depletion mode Metal-Nitride-Oxide-Semiconductor (MNOS) transistors are the load devices for a pair of active, n-channel, enhancement mode, Insulated Gate Field Effect Transistors (IGFETs) in a flip-flop circuit. N-channel enhancement mode access transistors also IGFETs connect the cell to the bit line and the bit line. Information is written in, and read, in volatile form conventionally. A +25 volt, 10 msec pulse applied to the gates of the depletion mode MNOS load devices transfers the data from the volatile mode to the nonvolatile mode.
Inventors
- 👤 Fritz L. Schurmeyer
- 👤 Charles R. Young
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:43
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356008; G; G11; G11C; G11C14/00; G11C16/00; G11C16/02; G11C16/04; G11C16/0466
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
239 words
A solid state RAM cell for a memory system having a bit line, a bit line, a word line, a gate line, and a drain line, the said cell comprising: a. an n-channel substrate; b. a first IGFET enhancement mode access transistor fabricated on the said n-channel substrate cooperating with the said bit line and the said word line; c. a second IGFET enhancement mode access transistor fabricated on the said n-channel substrate cooperating with the said bit line and the said word line; d. a first and a second IGFET enhancement mode, active transistors fabricated on the said n-channel substrate and cooperating with each other to provide a flip-flop; e. a first MNOS, IGFET depletion mode variable threshold transistor, fabricated on the said n-channel substrate, having a drain electrode connected to the said drain line, a gate electrode connected to the said gate line and a source electrode; f. a second MNOS, IGFET depletion mode variable threshold transistor, fabricated on the said n-channel substrate, having a drain electrode connected to the said drain line, a gate electrode connected to the said gate line, and a source electrode; g. means for connecting the said first access transistor and the said flip-flop to the said source electrode of the first variable threshold transistor, and the said second access transistor and the said flip-flop to the said source electrode of the second variable threshold transistor whereby a nonvolatile RAM is provided.
Claim 2
Dependent Claim
239 words
A solid state RAM cell for a memory system having a bit line, a bit line, a word line, a gate line, and a drain line, the said cell comprising: a. an n-channel substrate; b. a first IGFET enhancement mode access transistor fabricated on the said n-channel substrate cooperating with the said bit line and the said word line; c. a second IGFET enhancement mode access transistor fabricated on the said n-channel substrate cooperating with the said bit line and the said word line; d. a first and a second IGFET enhancement mode, active transistors fabricated on the said n-channel substrate and cooperating with each other to provide a flip-flop; e. a first MNOS, IGFET depletion mode variable threshold transistor, fabricated on the said n-channel substrate, having a drain electrode connected to the said drain line, a gate electrode connected to the said gate line and a source electrode; f. a second MNOS, IGFET depletion mode variable threshold transistor, fabricated on the said n-channel substrate, having a drain electrode connected to the said drain line, a gate electrode connected to the said gate line, and a source electrode; g. means for connecting the said first access transistor and the said flip-flop to the said source electrode of the first variable threshold transistor, and the said second access transistor and the said flip-flop to the said source electrode of the second variable threshold transistor whereby a nonvolatile RAM is provided.
Claim 3
Dependent Claim
129 words
In a random access memory device having enhancement mode active IGFET transistors with depletion mode MNOS variable threshold IGFET loads, all on n-channel material, and with a bit line, a bit line, a drain voltage line, a word line, and a gate line, the method of transferring data conventionally stored in volatile form to non-volatile storage, recovering the data, and erasing the device, comprising the steps of: a. applying a positive pulse to the said gate line for transferring the said data stored in volatile form to nonvolatile form; b. applying drain voltage, precharging the bit lines, and pulsing the word line to recover the said data after nonvolatile storage; and c. erasing the said memory device by applying a series of negative pulses to the said gate line.
Claim 4
Dependent Claim
129 words
In a random access memory device having enhancement mode active IGFET transistors with depletion mode MNOS variable threshold IGFET loads, all on n-channel material, and with a bit line, a bit line, a drain voltage line, a word line, and a gate line, the method of transferring data conventionally stored in volatile form to non-volatile storage, recovering the data, and erasing the device, comprising the steps of: a. applying a positive pulse to the said gate line for transferring the said data stored in volatile form to nonvolatile form; b. applying drain voltage, precharging the bit lines, and pulsing the word line to recover the said data after nonvolatile storage; and c. erasing the said memory device by applying a series of negative pulses to the said gate line.
References Cited (Backward Citations)
US3831155A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-23 | 1981-07-25 | 1982-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-23 | 1985-07-25 | 1986-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-23 | 1989-07-25 | 1990-01-24 | $7700.00 | Window Closed / Lapsed |