Patent US4159915A successfully refreshed from Google Patents.
US4159915A
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Method for fabrication vertical NPN and PNP structures utilizing ion-implantation
Assignee: International Business Machines Corp
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Filing: 1977-10-25
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Granted: 1979-07-03
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Expires: 1997-10-25
Abstract
Abstract A method is given for fabricating vertical NPN and PNP structures on the same semiconductor body. The method involves providing a monocrystalline semiconductor substrate having regions of monocrystalline silicon isolated from one another by isolation regions. Buried regions are formed overlapping the juncture of the substrate and epitaxial layer and are located in at least one of the regions of isolated monocrystalline silicon. The P base region in the NPN designated regions and a P reach-through in the PNP designated regions are formed simultaneously. The emitter region in the NPN regions and base contact region in the PNP regions are then formed simultaneously. The P emitter region in the PNP regions is then implanted by suitable ion implantation techniques. A Schottky Barrier collector contact in the PNP regions are formed. Electrical contacts are then made to the PNP and NPN transistor elements. A PNP device may be fabricated without the formation of an NPN device if it is so desired.
Inventors
- 👤 Narasipur G. Anantha
- 👤 Harsaran S. Bhatia
- 👤 James L. Walsh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:59
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D84/00; H10D84/01; H10D84/0112; H10D84/0119; H10D84/0121; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/611; H10D84/613; H10D84/641; H10D84/643; H10D84/67; H10D84/673; H10W; H10W20/00; H10W20/01; H10W20/021; Y; Y10; Y10S; Y10S148/00; Y10S148/131
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
226 words
Method for fabricating vertical NPN and PNP structures on the same semiconductor body comprising: providing a P monocrystalline semiconductor substrate; forming a pattern of N regions in said substrate; growing an N epitaxial layer on the surface of said substrate having said N regions; forming isolated regions of monocrystalline semiconductor in said substrate having said epitaxial layer thereon wherein said N regions are within the isolated regions designated to have NPN and PNP devices formed therein; implanting a buried P emitter region in the PNP designated regions; simultaneously forming the P base region in the NPN designated regions and a P emitter reachthrough in the PNP designated regions; simultaneously forming an N reachthrough to the collector region in the NPN regions and the N region under the PNP regions; simultaneously forming the N emitter region in the NPN regions, an N contact region to the collector reachthrough in the NPN regions, and N contact region to the N region under the PNP regions, and an N base contact region to the said N epitaxial layer in the PNP regions; forming a Schottky Barrier collector contact in the PNP regions; and forming electrical contacts to the NPN and PNP regions in said body, and to the N region under the PNP region for the junction isolation of the PNP structures from the rest of said semiconductor body.
Claim 2
Dependent Claim
226 words
Method for fabricating vertical NPN and PNP structures on the same semiconductor body comprising: providing a P monocrystalline semiconductor substrate; forming a pattern of N regions in said substrate; growing an N epitaxial layer on the surface of said substrate having said N regions; forming isolated regions of monocrystalline semiconductor in said substrate having said epitaxial layer thereon wherein said N regions are within the isolated regions designated to have NPN and PNP devices formed therein; implanting a buried P emitter region in the PNP designated regions; simultaneously forming the P base region in the NPN designated regions and a P emitter reachthrough in the PNP designated regions; simultaneously forming an N reachthrough to the collector region in the NPN regions and the N region under the PNP regions; simultaneously forming the N emitter region in the NPN regions, an N contact region to the collector reachthrough in the NPN regions, and N contact region to the N region under the PNP regions, and an N base contact region to the said N epitaxial layer in the PNP regions; forming a Schottky Barrier collector contact in the PNP regions; and forming electrical contacts to the NPN and PNP regions in said body, and to the N region under the PNP region for the junction isolation of the PNP structures from the rest of said semiconductor body.
Claim 3
Dependent Claim
28 words
The method of claim 1 wherein the said isolated regions of monocrystalline semiconductor are made by the formation of a pattern of dielectric isolation regions in said substrate.
Claim 4
Dependent Claim
38 words
The method of claim 2 wherein the said pattern of dielectric isolation regions include isolation regions for isolating the collector reach-through regions in NPN transistors and the reach-through to the PN junction isolating region in said PNP transistors.
Claim 5
Dependent Claim
34 words
The method of claim 1 wherein the ion implanted said buried P emitter is formed using 400 to 500 KeV and a dosage of 10 12 to 10 14 of boron ions/cm 2 .
Claim 6
Dependent Claim
33 words
The method of claim 1 wherein the said Schottky Barrier contact is formed by evaporating a high barrier metal over the entire wafer and forming metal silicides contacts, etching away excess said metal.
Claim 7
Dependent Claim
13 words
The method of claim 5 wherein said Schottky Barrier contact is platinum silicide.
Claim 8
Dependent Claim
15 words
The method of claim 1 wherein Schottky Barrier diodes are formed in said semiconductor body.
Claim 9
Dependent Claim
176 words
Method for fabricating vertical PNP structure on a semiconductor body comprising: providing a P monocrystalline semiconductor substrate; forming a pattern of N regions in said substrate; growing an N epitaxial layer on the surface of said substrate having said N regions; forming isolated regions of monocrystalline semiconductor in said substrate having said epitaxial layer thereon wherein said N regions are within the isolated regions designated to have PNP devices formed therein; implanting a buried P emitter region in the said PNP designated isolated regions; forming a P reachthrough to said buried P emitter region in said isolated regions; forming an N reachthrough to the said N region under the PNP regions; forming an N base contact region to the said N epitaxial layer in the said isolated regions; forming a Schottky Barrier collector contact in the PNP designated said isolated regions; and forming electrical contacts to the emitter, base and collector regions, and to the said N region under the PNP region for junction isolation of the PNP structures from the rest of said semiconductor body.
Claim 10
Dependent Claim
176 words
Method for fabricating vertical PNP structure on a semiconductor body comprising: providing a P monocrystalline semiconductor substrate; forming a pattern of N regions in said substrate; growing an N epitaxial layer on the surface of said substrate having said N regions; forming isolated regions of monocrystalline semiconductor in said substrate having said epitaxial layer thereon wherein said N regions are within the isolated regions designated to have PNP devices formed therein; implanting a buried P emitter region in the said PNP designated isolated regions; forming a P reachthrough to said buried P emitter region in said isolated regions; forming an N reachthrough to the said N region under the PNP regions; forming an N base contact region to the said N epitaxial layer in the said isolated regions; forming a Schottky Barrier collector contact in the PNP designated said isolated regions; and forming electrical contacts to the emitter, base and collector regions, and to the said N region under the PNP region for junction isolation of the PNP structures from the rest of said semiconductor body.
Claim 11
Dependent Claim
17 words
The method of claim 8 wherein an NPN transistor is simultaneously formed during the said PNP method.
Claim 12
Dependent Claim
15 words
The method of claim 8 wherein Schottky Barrier diodes are formed in said semiconductor body.
Claim 13
Dependent Claim
39 words
The method of claim 10 wherein the said Schottky Barrier diodes are formed by evaporating a low barrier metal on the silicon wherein said diodes are to be formed, followed by the evaporation of a current carrying metallurgy thereover.
Claim 14
Dependent Claim
21 words
The method of claim 10 wherein said Schottky Barrier diodes are formed within the same said isolated regions of monocrystalline semiconductor.
Claim 15
Dependent Claim
26 words
The method of claim 10 wherein the said Schottky Barrier diodes are formed from Ti/Al+Cu on silicon and said Schottky Barrier collector from PtSi/Ti/Al+Cu on silicon.
Claim 16
Dependent Claim
42 words
The method of claim 1 wherein Schottky barrier diodes are formed in said semiconductor body by evaporating a low barrier metal on the bare silicon wherein said diodes are to be formed, followed by the evaporation of a current carrying metallurgy thereover.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-07-02 | 1983-01-01 | 1983-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-07-02 | 1987-01-01 | 1987-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-07-02 | 1991-01-01 | 1991-07-03 | $7700.00 | Window Closed / Lapsed |