Schottky barrier device and circuit application

Claim 1

IN A HIGH CIRCUIT DENSITY DEVICE FABRICATED BY LARGE SCALE INTEGRATION TECHNIQUES ON A PLANAR SURFACE OF SILICON SEMICONDUCTOR SUBSTRATE, SAID DEVICE HAVING A PLURALITY OF CIRCUIT ELEMENTS, SAID CIRCUIT ELEMENTS INCLUDING TRANSISTORS, RESISTORS, AND SCHOTTKY BARRIER DIODES, SAID SUBSTRATE HAVING A SUBSTANTIALLY PLANAR SURFACE A THIN LAYER OF INSULATING MATERIAL ON SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE, SAID THIN LAYER OF INSULATING MATERIAL HAVING A PLURALITY OF DISCRETE WINDOWS EACH OF SAID WINDOWS OF SAID THIN INSULATING LAYER EXPOSING A PORTION OF SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE, EACH OF SAID WINDOWS PRO VIDING ACCESS TO SAID CIRCUIT ELEMENTS, A FIRST ONE OF SAID PLURALITY OF WINDOWS EXPOSING A FIRST SMALL SURFACE AREA OF SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE HAVING N- TYPE CONDUCTIVITY, A SECOND ONE OF SAID PLURALITY OF WINDOWS EXPOSING A SECOND SMALL SURFACE AREA OF SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE HAVING N + TYPE CONDUCTIVITY, SAID FIRST AND SECOND WINDOWS BEING CLOSELY DISPLACED IN SPACE ON SAID SURFACE OF SAID SEMICONDUCTOR SUBSTRATE, WHEREIN THE IMPROVEMENT COMPRISES: INTERCONNECTION METALLURGY MEANS FOR INTERCONNECTING SAID CIRCUIT ELEMENTS, SAID INTERCONNECTION MEANS CONSISTING ESSENTIALLY OF AN ALLOY OF 95% BY WEIGHT ALUMINUM AND 5% BY WEIGHT COPPER, SAID INTERCONNECTION MEANS BEING SUPERIMPOSED ON SAID THIN INSULATING LAYER AND INTEGRALLY CONNECTED THROUGH EACH OF SAID WINDOWS TO SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE, WHEREBY SAID FIRST AND SECOND SMALL SURFACE AREAS OF SAID PLANAR SURFACE OF SAID SEMICONDUCTOR SUBSTRATE RESPECTIVELY COMPRISE THE ANODE AND CATHODE AREA OF A SCHOTTKY BARRIER DIODE, AND SAID SCHOTTKY BARRIER DIODE IS INTEGRALLY CONNECTED TO SAID CIRCUIT ELEMENTS BY SAID INTERCONNECTION MEANS CONSISTING ESSENTIALLY OF SAID ALLOY OF ALUMINUM AND COPPER.