Localized oxidation enhancement for an integrated injection logic circuit

Claim 1

A process for forming an integrated circuit bipolar transistor logic structure capable of performing logical functions with lower voltage signals and capable of outputting from the integrated circuit higher voltage signals, comprising the steps of: forming a first buried region and a second buried region of a second cnductivity type in a semiconductor substrate of a first conductivity type; depositing an epitaxial layer of said second conductivity type over said first and second buried regions and said substrate; implanting ions in the surface of said epitaxial layer over said first buried region to induce crystalline damage sufficient to enhance the reactivity of the implanted region in an oxidation reaction; oxidizing the surface of said epitaxial layer forming a relatively thick oxide in said implanted region thereby forming a locally thinner region in the epitaxial layer over said first buried region, and a thicker epitaxial region over said second buried region; forming a first and a second base regions of said first conductivity type in said epitaxial layer at first and second respective separation distances over said first and second buried regions, respectively; and forming a collector region in said first base region and an emitter in said second base region, of said second conductivity types; whereby said thinner epitaxial layer over said first buried region imparts a lower charge storage characteristic and a higher injection efficiency for an upward injecting transistor and said thicker epitaxial layer over said second buried region imparts a higher voltage breakdown characteristic for a downward injecting transistor.