PROM circuit board programmer

Claim 1

A system for programming a plurality of integrated programmable read-only memory circuits each of said integrated circuit including a plurality of single-bit storage cells, address means for addressing said single-bit storage cells, data receiving means for receiving single bits of data to be non-volatilely stored in address storage cells and data output means for reading single bits of data from addressed storage cells, said system comprising: (a) means for providing sets of data for non-volatile storage in the integrated read-only memory circuits; (b) memory address generating means for generating cell addresses, in predetermined sequences, for the address means of each of said integrated memory circuits; (c) means for coupling said memory address generating means to the address means of each of said integrated memory circuits; (d) chip select means for generating signals to select and enable one-at-a-time said integrated memory circuits in a predetermined sequence; (e) means for coupling said chip select means to said integrated memory circuits; (f) comparator means; (g) means for coupling said comparator means to the outputs of said integrated memory circuits, said comparator means for receiving bits of data from addressed memory cells of enabled ones of said integrated memory circuits and comparing such received bits of data with respective bits of data of said sets of data to determine whether the compared bits are of states which meet predetermined criteria; and (h) means responsive to said comparator means for selectively supplying a programming voltage to the integrated memory circuit selected by said chip select means to non-volatilely alter the state of the addressed single-bit storage cell thereof when the bits of data compared by said comparator means do not meet said predetermined criteria.

Claim 2

A system for programming a plurality of integrated programmable read-only memory circuits each of said integrated circuit including a plurality of single-bit storage cells, address means for addressing said single-bit storage cells, data receiving means for receiving single bits of data to be non-volatilely stored in address storage cells and data output means for reading single bits of data from addressed storage cells, said system comprising: (a) means for providing sets of data for non-volatile storage in the integrated read-only memory circuits; (b) memory address generating means for generating cell addresses, in predetermined sequences, for the address means of each of said integrated memory circuits; (c) means for coupling said memory address generating means to the address means of each of said integrated memory circuits; (d) chip select means for generating signals to select and enable one-at-a-time said integrated memory circuits in a predetermined sequence; (e) means for coupling said chip select means to said integrated memory circuits; (f) comparator means; (g) means for coupling said comparator means to the outputs of said integrated memory circuits, said comparator means for receiving bits of data from addressed memory cells of enabled ones of said integrated memory circuits and comparing such received bits of data with respective bits of data of said sets of data to determine whether the compared bits are of states which meet predetermined criteria; and (h) means responsive to said comparator means for selectively supplying a programming voltage to the integrated memory circuit selected by said chip select means to non-volatilely alter the state of the addressed single-bit storage cell thereof when the bits of data compared by said comparator means do not meet said predetermined criteria.

Claim 7

A system for programming a plurality of integrated programmable read-only memory circuits, each of said integrated circuits including a plurality of single-bit storage cells, address means for addressing said single-bit storage cells, data receiving means for receiving single bits of data to be non-volatilely stored in addressed storage cells and data output means for reading single bits of data from addressed storage cells, said system comprising: (a) means for providing sets of data for non-volatile storage in the integrated read-only memory circuits; (b) memory address generating means for generating cell addresses, in a predetermined sequence, for the address means of each of said integrated memory circuits; (c) means for coupling said memory address generating means to the address means of each of said integrated memory circuits; (d) a controllable dual voltage supply means for selectively providing, at an output thereof, a relatively high programming voltage sufficient to non-volatilely alter the state of an addressed storage cell of said integrated read-only memory circuits and, alternately, a relatively low read voltage; (e) chip select means for generating signals to select and enable one-at-a-time said integrated memory circuits in a predetermined sequence, said chip select means being coupled to the output of said controlled dual voltage supply for supplying the selected voltage to the selected one of said integrated read-only memory circuits; (f) means for coupling said chip select means to said integrated memory circuits; (g) comparator means; (h) means for coupling said comparator means to the outputs of said integrated memory circuits, said comparator means for receiving bits of data from addressed memory cells of integrated memory circuits enabled with said relatively low read voltage via said chip select means and comparing such received bits with respective bits of said sets of data to determine whether the compared bits are of states which meet a predetermined criteria; and (i) means responsive to said comparator means for controlling said controllable dual voltage supply means to supply said relatively high programming voltage to the selected one of said integrated memory circuits for non-volatilely altering the state of the addressed single bit storage cell thereof when the bits of data compared by said comparator means do not meet said predetermined criteria.

Claim 8

A system for programming a plurality of integrated programmable read-only memory circuits, each of said integrated circuits including a plurality of single-bit storage cells, address means for addressing said single-bit storage cells, data receiving means for receiving single bits of data to be non-volatilely stored in addressed storage cells and data output means for reading single bits of data from addressed storage cells, said system comprising: (a) means for providing sets of data for non-volatile storage in the integrated read-only memory circuits; (b) memory address generating means for generating cell addresses, in a predetermined sequence, for the address means of each of said integrated memory circuits; (c) means for coupling said memory address generating means to the address means of each of said integrated memory circuits; (d) a controllable dual voltage supply means for selectively providing, at an output thereof, a relatively high programming voltage sufficient to non-volatilely alter the state of an addressed storage cell of said integrated read-only memory circuits and, alternately, a relatively low read voltage; (e) chip select means for generating signals to select and enable one-at-a-time said integrated memory circuits in a predetermined sequence, said chip select means being coupled to the output of said controlled dual voltage supply for supplying the selected voltage to the selected one of said integrated read-only memory circuits; (f) means for coupling said chip select means to said integrated memory circuits; (g) comparator means; (h) means for coupling said comparator means to the outputs of said integrated memory circuits, said comparator means for receiving bits of data from addressed memory cells of integrated memory circuits enabled with said relatively low read voltage via said chip select means and comparing such received bits with respective bits of said sets of data to determine whether the compared bits are of states which meet a predetermined criteria; and (i) means responsive to said comparator means for controlling said controllable dual voltage supply means to supply said relatively high programming voltage to the selected one of said integrated memory circuits for non-volatilely altering the state of the addressed single bit storage cell thereof when the bits of data compared by said comparator means do not meet said predetermined criteria.

Claim 12

A system for copying the contents of a volatile memory into a non-volative memory, said non-volatile memory being comprised of a plurality of integrated programmable read-only memory circuits, each of said integrated circuits including a plurality of single-bit storage cells, address means for addressing said single-bit storage cells, data receiving means for receiving single bits of data from addressed storage cells, said system comprising: (a) an addressable buffer memory means; (b) memory address generating means for generating respective addresses of said volatile memory means, said buffer memory means and said integrated read-only memory circuits; (c) data bus means for coupling said volatile memory means to said buffer memory means; (d) means for coupling said memory address generating means to said volatile memory and to said buffer memory means for controlling the addressing of said buffer memory means in synchronism with the addressing of said volatile memory, the contents of addressed locations of said volatile memory being transferrable over said data bus means into addressed locations of said buffer memory means; (e) means including chip select means for coupling said address generating means to said integrated read-only memory circuits, said chip select means being responsive to said address generating means for selecting and enabling one-at-a-time said integrated memory circuits in a predetermined sequence and said address means being responsive to said address generating means for addressing single bit storage cells of each of said integrated memory circuits in a predetermined sequence, said programmable read-only memory circuits being thereby addressable in synchronism with the addressing of said buffer memory means for transferring the contents of said buffer memory means into said programmable read-only memory means; and (f) means for selectively supplying a read voltage and a programming voltage to the integrated read-only memory circuit selected by said chip select means, said read voltage to read the contents of the addressed single-bit storage cell without altering the state thereof and said programming voltage to non-volatilely alter the state of the addressed single-bit storage cell.

Claim 13

A system for copying the contents of a volatile memory into a non-volative memory, said non-volatile memory being comprised of a plurality of integrated programmable read-only memory circuits, each of said integrated circuits including a plurality of single-bit storage cells, address means for addressing said single-bit storage cells, data receiving means for receiving single bits of data from addressed storage cells, said system comprising: (a) an addressable buffer memory means; (b) memory address generating means for generating respective addresses of said volatile memory means, said buffer memory means and said integrated read-only memory circuits; (c) data bus means for coupling said volatile memory means to said buffer memory means; (d) means for coupling said memory address generating means to said volatile memory and to said buffer memory means for controlling the addressing of said buffer memory means in synchronism with the addressing of said volatile memory, the contents of addressed locations of said volatile memory being transferrable over said data bus means into addressed locations of said buffer memory means; (e) means including chip select means for coupling said address generating means to said integrated read-only memory circuits, said chip select means being responsive to said address generating means for selecting and enabling one-at-a-time said integrated memory circuits in a predetermined sequence and said address means being responsive to said address generating means for addressing single bit storage cells of each of said integrated memory circuits in a predetermined sequence, said programmable read-only memory circuits being thereby addressable in synchronism with the addressing of said buffer memory means for transferring the contents of said buffer memory means into said programmable read-only memory means; and (f) means for selectively supplying a read voltage and a programming voltage to the integrated read-only memory circuit selected by said chip select means, said read voltage to read the contents of the addressed single-bit storage cell without altering the state thereof and said programming voltage to non-volatilely alter the state of the addressed single-bit storage cell.