US3602899A
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Associative memory system with match,no match and multiple match resolution
Assignee: International Business Machines Corp
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Filing: 1969-06-20
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Granted: 1971-08-31
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Expires: 1989-06-20
Abstract
Abstract An associative memory matrix having a writable portion made up of bistable memory cells and a read-only portion made up of monostable memory cells. The memory may be used as a conventional memory by placing an address in the address field of an entry register, masking out all other bits and performing a match interrogation with the unmasked bits. Since the contents of the address portion (read-only memory) of each stored word are unique, the interrogation results in a single match at the location containing the address sought. Included is a circuit for determining whether no match, one match, or a multiple match has occurred.
Inventors
- 👤 Arwin B Lindquist
- 👤 Wilbur D Pricer
- 👤 Robert R Seeber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 02:15
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
370 words
In a memory including a matrix of memory cells, rows of which correspond to words; columns of which correspond to bit positions within each word, and iN which each memory cell is of a type which has a word drive line coupled to each cell in a row which upon energization produces a signal on a 0-bit sense line or a 1bit sense line of a pair of such lines for each cell in said row depending upon the state of the cell, and in which said 0-bit sense lines in a column are coupled to a common bit sense 0 output, and said 1-bit sense lines in a column are coupled to a common bit sense 1 output, the improvement comprising: an address portion of said matrix for storing an address field in each word stored in said memory, the bits in said address field set to represent unique addresses for each word, each address differing from each other word address by the state of at least one bit position in said field; control means for energizing none, one, or a plurality of said word drive lines for reading words from said matrix thereby producing signals on the 1 lines or the 0 lines depending upon the state of the cells; means coupled to the common bit sense 0 outputs and the common bit sense 1 outputs of said address portion for combining the 1 and 0-bit sense 0-of each column of said address portion to yield a first output in response to both bit sense outputs being energized in any pair, thus indicating the reading of a plurality of words; means coupled to the common bit sense 0 output and the common bit sense 1 output of one column of cells in said matrix for combining the 1- and 0-bit sense outputs to yield a second output if either one of the outputs is energized thus indicating the reading of at least one word; and means combining said first output and said second output to thereby produce a third output whenever the first output is not energized and the second output is energized, to thereby yield a signal indicating the reading of only one word in said matrix.
Claim 2
Dependent Claim
370 words
In a memory including a matrix of memory cells, rows of which correspond to words; columns of which correspond to bit positions within each word, and iN which each memory cell is of a type which has a word drive line coupled to each cell in a row which upon energization produces a signal on a 0-bit sense line or a 1bit sense line of a pair of such lines for each cell in said row depending upon the state of the cell, and in which said 0-bit sense lines in a column are coupled to a common bit sense 0 output, and said 1-bit sense lines in a column are coupled to a common bit sense 1 output, the improvement comprising: an address portion of said matrix for storing an address field in each word stored in said memory, the bits in said address field set to represent unique addresses for each word, each address differing from each other word address by the state of at least one bit position in said field; control means for energizing none, one, or a plurality of said word drive lines for reading words from said matrix thereby producing signals on the 1 lines or the 0 lines depending upon the state of the cells; means coupled to the common bit sense 0 outputs and the common bit sense 1 outputs of said address portion for combining the 1 and 0-bit sense 0-of each column of said address portion to yield a first output in response to both bit sense outputs being energized in any pair, thus indicating the reading of a plurality of words; means coupled to the common bit sense 0 output and the common bit sense 1 output of one column of cells in said matrix for combining the 1- and 0-bit sense outputs to yield a second output if either one of the outputs is energized thus indicating the reading of at least one word; and means combining said first output and said second output to thereby produce a third output whenever the first output is not energized and the second output is energized, to thereby yield a signal indicating the reading of only one word in said matrix.
Claim 3
Dependent Claim
21 words
The memory matrix of claim 1 wherein said address portion comprises read-only memory cells, set to nondestructively store said unique addresses.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-30 | 1975-03-01 | 1975-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-30 | 1979-03-01 | 1979-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-30 | 1983-03-01 | 1983-08-31 | $7700.00 | Window Closed / Lapsed |