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Patent US4079506A successfully refreshed from Google Patents.
US4079506A
Expired / Lapsed
US
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Method of preparing a dielectric-isolated substrate for semiconductor integrated circuitries
Assignee: Hitachi Ltd
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Filing: 1975-12-05
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Granted: 1978-03-21
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Expires: 1995-12-05
Abstract
Abstract In the preparation of a dielectric-isolated substrate for semiconductor integrated circuits which comprises a plurality of silicon single crystalline islands in which circuit elements are formed, a region made of an alternate laminate of silicon polycrystalline layers and silicon oxide films for supporting the plurality of silicon single crystalline islands, and a silicon oxide film interposed between the silicon single crystalline islands and the support region for isolating each of the silicon single crystalline islands from the remaining ones and the support region, the formation of three to twelve silicon polycrystalline layers in the support region can remarkably reduce the bending of the substrate resulting from the growth stress of the silicon polycrystalline layers or from the difference in thermal expansion coefficients between the single crystalline silicon and the polycrystalline silicon, and therefore produces a dielectric-isolated substrate showing little bending.
Inventors
- 👤 Takaya Suzuki
- 👤 Seturoo Yagyuu
- 👤 Akio Mimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:44
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/043; Y10S148/051; Y10S148/085; Y10S148/097; Y10S148/122; Y10S148/15
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
153 words
A method of manufacturing a dielectric-isolated substrate for semiconductor integrated circuits consisting of: (a) forming spaced-apart grooves in one principal plane surface of a silicon single crystalline wafer; (b) forming a dielectric film on the one principal plane surface of said silicon single crystalline wafer having said spaced-apart grooves formed therein; (c) forming on said dielectric film a support region made of an alternate multiple layer structure of n silicon polycrystalline layers each having the same thickness and n-1 silicon oxide layers each having the same thickness, where n is an integer from 3 to 12 inclusive; (d) removing material from the opposite principal plane surface of the silicon single crystalline wafer until said spaced-apart grooves are exposed and plural single crystalline islands isolated by said dielectric film are formed; whereby support for the dielectric-isolated regions is provided entirely by the alternate multiple layer structure of said support region with substantially no curvature.
Claim 2
Independent Claim
153 words
A method of manufacturing a dielectric-isolated substrate for semiconductor integrated circuits consisting of: (a) forming spaced-apart grooves in one principal plane surface of a silicon single crystalline wafer; (b) forming a dielectric film on the one principal plane surface of said silicon single crystalline wafer having said spaced-apart grooves formed therein; (c) forming on said dielectric film a support region made of an alternate multiple layer structure of n silicon polycrystalline layers each having the same thickness and n-1 silicon oxide layers each having the same thickness, where n is an integer from 3 to 12 inclusive; (d) removing material from the opposite principal plane surface of the silicon single crystalline wafer until said spaced-apart grooves are exposed and plural single crystalline islands isolated by said dielectric film are formed; whereby support for the dielectric-isolated regions is provided entirely by the alternate multiple layer structure of said support region with substantially no curvature.
Claim 3
Dependent Claim
68 words
A method according to claim 1, wherein said silicon single crystalline wafer is 300 ± 100 μ in thickness, said support region is 200 μ to 500 μ in thickness, said silicon polycrystalline layers and silicon oxide films constituting said support region undergo vapor phase growth at temperatures from 1100° C to 1250° C and at growth rate for the silicon polycrystalline layers of 1 to 8 μ/min.
Claim 4
Dependent Claim
59 words
A method according to claim 2, wherein for a substrate 50 mm in diameter, the number n of silicon polycrystalline layers is determined by the following equation: H ≃ A · n + B, where H represents a permissible maximum deflection, A a constant defined by A≃- 18 (μ/one layer) and B a constant defined by B≃60 to 200(μ).
Claim 5
Dependent Claim
36 words
A method according to claim 1, wherein each of silicon polycrystalline layers of said support region is about 45 μ in thickness, and each of silicon oxide films is 0.3 μ to 2 μ in thickness.
Claim 6
Independent Claim
118 words
A method of preparing a dielectric-isolated substrate for semiconductor integrated circuitries consisting of: forming spaced grooves in one principal plane surface of a silicon single crystalline wafer; forming a dielectric film on the one principal plane surface of the silicon single crystalline wafer formed with the spaced grooves; forming on the dielectric film a support region of an alternate multiple layer structure of silicon oxide films and silicon polycrystalline layers, of equal thickness the number of said silicon polycrystalline layers being 3 to 12; polishing the opposite principal plane surface of the silicon single crystalline wafer until the spaced grooves are exposed to the outside and numerous silicon single crystalline islands isolated with the dielectric film are formed.
Claim 7
Independent Claim
118 words
A method of preparing a dielectric-isolated substrate for semiconductor integrated circuitries consisting of: forming spaced grooves in one principal plane surface of a silicon single crystalline wafer; forming a dielectric film on the one principal plane surface of the silicon single crystalline wafer formed with the spaced grooves; forming on the dielectric film a support region of an alternate multiple layer structure of silicon oxide films and silicon polycrystalline layers, of equal thickness the number of said silicon polycrystalline layers being 3 to 12; polishing the opposite principal plane surface of the silicon single crystalline wafer until the spaced grooves are exposed to the outside and numerous silicon single crystalline islands isolated with the dielectric film are formed.
Claim 8
Dependent Claim
77 words
A method of preparing a dielectric-isolated substrate for semiconductor integrated circuitries according to claim 2, wherein said silicon single crystalline wafer is 300 ± 100 μ in thickness, said support region is 200 μ to 500 μ in thickness, said silicon polycrystalline layers and silicon oxide films constituting said support region undergo vapor phase growth at temperatures from 1100° C to 1250° C and at growth rate for the silicon polycrystalline layers of 1 to 8 μ/min.
Claim 9
Dependent Claim
71 words
A method of preparing a dielectric-isolated substrate for semiconductor integrated circuitries according to claim 3, wherein for a substrate 50 mm in diameter, the number n of silicon polycrystalline layers is determined by the following equation: H ≃ A · n + B, where H represents a permissible maximum deflection, A a constant defined by A ≃ - 18 (μ/one layer) and B a constant defined by B≃60 to 200 (μ).
Claim 10
Dependent Claim
45 words
A method of preparing a dielectric-isolated substrate for semiconductor integrated circuitries according to claim 2, wherein each of silicon polycrystalline layers of said support region is about 45 μ in thickness, and each of silicon oxide films is 0.3 μ to 2 μ in thickness.
Claim 11
Independent Claim
186 words
A method of preparing a dielectric-isolated substrate for semiconductor integrated circuitries which substrate comprises a plurality of silicon single crystalline islands provided for circuit elements formed therein, a support region of an alternate multiple layer structure of silicon polycrystalline layers and silicon oxide films for supporting the plurality of silicon single crystalline islands, and a dielectric film for effecting electrical isolation between said single crystalline islands and between said support region and single crystalline islands, wherein said method consists of growing silicon as polycrystalline silicon by heating a derivative of monosilane having a chemical composition of SiH m Cl n in an atmosphere of hydrogen wherein 0≦m≦3 and 1≦n≦4, and growing silicon oxide by heating said derivative of monosilane in a mixed gas of hydrogen and oxygen, said first and second steps being conducted alternately and repeatedly at the same temperature for vapor growth in the same reactor vessel for vapor growth to form said support region, the number of silicon polycrystalline layers included in said support region lying in a range of 3 to 12 inclusive, each of said polycrystalline layers having the same thickness.
Claim 12
Independent Claim
186 words
A method of preparing a dielectric-isolated substrate for semiconductor integrated circuitries which substrate comprises a plurality of silicon single crystalline islands provided for circuit elements formed therein, a support region of an alternate multiple layer structure of silicon polycrystalline layers and silicon oxide films for supporting the plurality of silicon single crystalline islands, and a dielectric film for effecting electrical isolation between said single crystalline islands and between said support region and single crystalline islands, wherein said method consists of growing silicon as polycrystalline silicon by heating a derivative of monosilane having a chemical composition of SiH m Cl n in an atmosphere of hydrogen wherein 0≦m≦3 and 1≦n≦4, and growing silicon oxide by heating said derivative of monosilane in a mixed gas of hydrogen and oxygen, said first and second steps being conducted alternately and repeatedly at the same temperature for vapor growth in the same reactor vessel for vapor growth to form said support region, the number of silicon polycrystalline layers included in said support region lying in a range of 3 to 12 inclusive, each of said polycrystalline layers having the same thickness.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-20 | 1981-09-19 | 1982-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-20 | 1985-09-19 | 1986-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-20 | 1989-09-19 | 1990-03-21 | $7700.00 | Window Closed / Lapsed |