Semiconductor structure

Claim 2

In a semiconductor structure, a support structure, a plurality of discrete semiconductor islands mounted on said support structure, said islands having surfaces lying in a substantially common plane and facing away from said support structure and insulating material formed of a material different from the support structure intimately bonded to said support structure and said islands and electrically isolating said islands from each other and from the support structure, said support structure having recesses therein receiving said islands with said insulating material bonded thereto and having raised portions extending between said islands, said insulating material being capable of withstanding temperatures required for diffusion of impurities into said islands, said insulating material including diffused isolation fences.

Claim 3

In a semiconductor structure, a support structure having a grid structure formed therein, insulating material of a material different from the support structure disposed on the support structure to form an additional grid structure bonded to the first named grid structure and a plurality of islands of semiconductor material embedded in the additional grid structure and electrically isolated from each other and from the support structure, certain of said islands having surfaces lying in a common plane, said insulating material including a layer which is spaced from said surfaces of the islands and diffused fences extending from said surfaces to said layer.

Claim 4

In a semiconductor structure, a support structure having a grid structure formed therein, insulating material of a material different from the support structure disposed on the support structure to form an additional grid structure bonded to the first named grid structure and a plurality of islands of semiconductor material embedded in the additional grid structure and electrically isolated from each other and from the support structure, certain of said islands having surfaces lying in a common plane, said insulating material including a layer which is spaced from said surfaces of the islands and diffused fences extending from said surfaces to said layer.

Claim 5

A semiconductor structure as in claim 2 together with active and passive devices formed in the islands and means interconnecting said active and passive devices.

Claim 6

In a semiconductor structure, a support structure having a grid structure formed therein, insulating material of a material different from the support structure disposed on the support structure to form an additional grid structure bonded to the first named grid structure and a plurality of islands of semiconductor material embedded in the additional grid structure and electrically isolated from each other and from the support structure, said islands having first and second opposed surfaces, first and second semiconductor devices formed in at least one island, said first semiconductor device having a junction extending to said first surface and said second semiconductor device having a junction extending to said second surface of said one island.

Claim 7

In a semiconductor structure, a support structure having a grid structure formed therein, insulating material of a material different from the support structure disposed on the support structure to form an additional grid structure bonded to the first named grid structure and a plurality of islands of semiconductor material embedded in the additional grid structure and electrically isolated from each other and from the support structure, said islands having first and second opposed surfaces, first and second semiconductor devices formed in at least one island, said first semiconductor device having a junction extending to said first surface and said second semiconductor device having a junction extending to said second surface of said one island.

Claim 8

In a semiconductor structure, a semiconductor body of monocrystalline silicon, a layer of insulating material formed of silicon dioxide disposed on the body, and A support structure of polycrystalline silicon disposed on the insulating material, said semiconductor body, said layer and said support structure being intimately bonded together to form a solid unitary mass, said support structure being formed with a grid structure with said layer of insulating material overlying said grid structure, said semiconductor body being recessed within said layer of insulating material, and a layer of material substantially harder than the semiconductor body and the layer of insulating material carried by the semiconductor structure and serving as a lapping stop to define a plane to determine the thickness of the semiconductor body recessed within said layer of insulating material.

Claim 9

In a semiconductor structure, a semiconductor body of monocrystalline silicon, a layer of insulating material formed of silicon dioxide disposed on the body, and A support structure of polycrystalline silicon disposed on the insulating material, said semiconductor body, said layer and said support structure being intimately bonded together to form a solid unitary mass, said support structure being formed with a grid structure with said layer of insulating material overlying said grid structure, said semiconductor body being recessed within said layer of insulating material, and a layer of material substantially harder than the semiconductor body and the layer of insulating material carried by the semiconductor structure and serving as a lapping stop to define a plane to determine the thickness of the semiconductor body recessed within said layer of insulating material.

Claim 10

In a semiconductor structure, a support structure, a plurality of discrete semiconductor islands mounted on the support structure, said islands having surfaces lying in a substantially common plane and facing away from said support structure and insulating material formed of a material different from the support structure intimately bonded to said support structure and said islands and electrically isolating said islands from each other and from the support structure, said support structure having recesses and receiving said islands with said insulating material bonded thereto and having raised portions extending between the islands, said insulating material being capable of withstanding temperatures required for diffusion of impurities into said islands, at least one of said islands having two opposed surfaces, first and second semiconductor devices formed in said one island said first device having a junction extending to one of said opposed surfaces and the second device having a junction extending to the other of said opposed surfaces.

Claim 11

In a semiconductor structure, a support structure, a plurality of discrete semiconductor islands mounted on the support structure, said islands having surfaces lying in a substantially common plane and facing away from said support structure and insulating material formed of a material different from the support structure intimately bonded to said support structure and said islands and electrically isolating said islands from each other and from the support structure, said support structure having recesses and receiving said islands with said insulating material bonded thereto and having raised portions extending between the islands, said insulating material being capable of withstanding temperatures required for diffusion of impurities into said islands, at least one of said islands having two opposed surfaces, first and second semiconductor devices formed in said one island said first device having a junction extending to one of said opposed surfaces and the second device having a junction extending to the other of said opposed surfaces.

Claim 12

A semiconductor circuit arrangement comprising a body having portions of a semiconductor material of first conductivity type having surface areas and having portions of inlaid insulating material to form complementary patterns defining a planar topology, active circuit elements formed within selected ones of said surface areas, said active circuit elements being formed by P/N junctions extending to said surface areas, a layer of insulating material overlying said surface areas and said portions of inlaid insulating material and means for functionally interconnecting said active devices to form an oeprative circuit arrangement, said interconnecting means including first conductive means passing over said patterns and extending through said layer of insulating material and second conductive means passing beneath said patterns.

Claim 13

A semiconductor circuit arrangement comprising a body having portions of a semiconductor material of first conductivity type having surface areas and having portions of inlaid insulating material to form complementary patterns defining a planar topology, active circuit elements formed within selected ones of said surface areas, said active circuit elements being formed by P/N junctions extending to said surface areas, a layer of insulating material overlying said surface areas and said portions of inlaid insulating material and means for functionally interconnecting said active devices to form an oeprative circuit arrangement, said interconnecting means including first conductive means passing over said patterns and extending through said layer of insulating material and second conductive means passing beneath said patterns.

Claim 14

A semiconductor circuit arrangement as defined in claim 7 wherein said first conductive means are formed of thin metallic members.

Claim 15

A semiconductor circuit arrangement as defined in claim 7 wherein said second conductive means passing beneath said patterns is continuous between selected ones of said surface portions whereby a crossunder connection is defined with said first conductive means.

Claim 16

A circuit arrangement comprising a body having a predetermined pattern of recesses defining an array of first structures having planar surface areas, dielectric material formed within said recesses and defining a substantially planar topology with said planar surface areas of said first structures, said first structures being electrically isolated one from the other, active circuit elements formed in said first structures, said active circuit elements including P/N junctions extending to said planar surface areas, a layer of insulating material overlying said planar surface areas and said dielectric material and means including first conductive means formed over said layer of insulating material and over said dielectric material and extending through said layer of insulating material to make contact to said active elements and second conductive means formed under said dielectric material for functionally interconnecting said active circuit elements.

Claim 17

A circuit arrangement comprising a body having a predetermined pattern of recesses defining an array of first structures having planar surface areas, dielectric material formed within said recesses and defining a substantially planar topology with said planar surface areas of said first structures, said first structures being electrically isolated one from the other, active circuit elements formed in said first structures, said active circuit elements including P/N junctions extending to said planar surface areas, a layer of insulating material overlying said planar surface areas and said dielectric material and means including first conductive means formed over said layer of insulating material and over said dielectric material and extending through said layer of insulating material to make contact to said active elements and second conductive means formed under said dielectric material for functionally interconnecting said active circuit elements.

Claim 18

A circuit arrangement comprising a planar sEmiconductor body of first conductivity type, discrete regions of semiconductor material of second conductivity type carried by said planar body having planar surface areas, dielectric means formed on said planar body and between said discrete regions to define a planar topology with said planar surface areas and wherein said planar surface areas are exposed, active circuit elements formed in said discrete areas of second conductivity type and having P/N junctions extending to said planar surface areas, a layer of insulating material overlying said discrete regions and said dielectric means and conductive means passing beneath and over said dielectric means for functionally interconnecting said circuit elements into an operative arrangement, said conductive means passing over said dielectric means extending through said layer of insulating material and making contact to said active circuit elements.

Claim 19

A circuit arrangement comprising a planar sEmiconductor body of first conductivity type, discrete regions of semiconductor material of second conductivity type carried by said planar body having planar surface areas, dielectric means formed on said planar body and between said discrete regions to define a planar topology with said planar surface areas and wherein said planar surface areas are exposed, active circuit elements formed in said discrete areas of second conductivity type and having P/N junctions extending to said planar surface areas, a layer of insulating material overlying said discrete regions and said dielectric means and conductive means passing beneath and over said dielectric means for functionally interconnecting said circuit elements into an operative arrangement, said conductive means passing over said dielectric means extending through said layer of insulating material and making contact to said active circuit elements.

Claim 20

A circuit arrangement as defined in claim 11 wherein said conductive means over said dielectric means are defined by thin metallic conductors.

Claim 21

A semiconductor device, comprising: a support body having first and second major surfaces, a layer of insulating material overlying said support body on said first major surface, a body of single crystalline semiconductor material embedded in said layer of insulating material and supported by said support body, said body of semiconductor material having top and bottom surfaces generally parallel to said first major surface of the substrate, said body of semiconductor material comprising at least two zones having impurities of opposite conductivity types therein with a junction defining said at least two zones, said junction extending between said top and bottom surfaces, a layer of insulating material overlying said top surface and conductive means extending through said insulating layer and making contact to said two zones.

Claim 22

A semiconductor device, comprising: a support body having first and second major surfaces, a layer of insulating material overlying said support body on said first major surface, a body of single crystalline semiconductor material embedded in said layer of insulating material and supported by said support body, said body of semiconductor material having top and bottom surfaces generally parallel to said first major surface of the substrate, said body of semiconductor material comprising at least two zones having impurities of opposite conductivity types therein with a junction defining said at least two zones, said junction extending between said top and bottom surfaces, a layer of insulating material overlying said top surface and conductive means extending through said insulating layer and making contact to said two zones.