Thyristor with gold doping profile

Claim 2

A semiconductor switching device comprising a semiconductor wafer including four semiconductor regions disposed in such a relationship that each of said four semiconductor regions exhibits a different conductivity type from those of adjacent ones, wherein one central region is composed of a material having a higher resistivity than the other central region and both having therebetween a first junction centrally positioned of three PN junctions formed between said four semiconductor regions and a second junction positioned on one of the ends of said tHree PN junctions, and wherein said semiconductor wafer includes therein impurities for controlling the lifetime of carriers injected therein during use of the device, and wherein the impurity concentration of the portion of said central region adjacent to said first junction has a value greater than 1.2 times that of the impurity concentration of the portion of the central region adjacent to said second junction.

Claim 3

A semiconductor switching device as claimed in claim 1, wherein said semiconductor wafer is composed mainly of silicon, and said impurities for controlling the lifetime of the carriers is composed of one element selected from the group consisting of gold, iron and copper.

Claim 4

A semiconductor switching device as claimed in claim 1, wherein said impurity concentration of said central region of higher resistivity has its maximum value at the portion adjacent to said first junction and its minimum value at the portion adjacent to said second junction.

Claim 5

A semiconductor switching device as claimed in claim 1, wherein said impurity concentration of the central region of higher resistivity has its maximum value at the portion adjacent to said first junction and decreases continuously toward said second junction to exhibit its minimum value at the portion adjacent to said second junction.

Claim 6

A semiconductor switching device comprising a semiconductor wafer having a first and a second end surfaces substantially parallel to each other and including four semiconductor regions disposed in such a relationship that each of said four semiconductor regions exhibits a different conductivity type from that of adjacent ones, a first end region of said four semiconductor regions defining said first end surface, a second end region thereof inserted into a first central region adjacent to the same to define the second end surface with said first central region, and a second central region disposed between said first end region and said first central region, a central PN junction being formed between said first and said second central regions, a first end PN junction formed between said first central region and said second end region, and a second end PN junction formed between said second central region and said first end region, and said wafer including therein impurities for controlling the lifetime of carriers injected therein during use of the device, and wherein the concentration of said impurities in the portion of said second central region adjacent to said central PN junction has a value greater than 1.2 times the concentration of said impurities in the portion of said second central region adjacent to said end PN junction.

Claim 7

A semiconductor switching device comprising a semiconductor wafer having a first and a second end surfaces substantially parallel to each other and including four semiconductor regions disposed in such a relationship that each of said four semiconductor regions exhibits a different conductivity type from that of adjacent ones, a first end region of said four semiconductor regions defining said first end surface, a second end region thereof inserted into a first central region adjacent to the same to define the second end surface with said first central region, and a second central region disposed between said first end region and said first central region, a central PN junction being formed between said first and said second central regions, a first end PN junction formed between said first central region and said second end region, and a second end PN junction formed between said second central region and said first end region, and said wafer including therein impurities for controlling the lifetime of carriers injected therein during use of the device, and wherein the concentration of said impurities in the portion of said second central region adjacent to said central PN junction has a value greater than 1.2 times the concentration of said impurities in the portion of said second central region adjacent to said end PN junction.

Claim 8

A semiconductor switching device as claimed in claim 5, comprising a first electrode disposed on said first end surface in ohmic contact with said first end region, a second electrode disposed on said second end surface in ohmic contact with said second end region and a third electrode in ohmic contact with said first central region.

Claim 9

A semiconductor switching device as claimed in claim 6, wherein said second end region has an annular shape and the portion of said first central region encircled by said second end region is in ohmic contact with said third electrode.

Claim 10

A semiconductor switching device as claimed in claim 5, wherein said wafer is composed mainly of silicon, and said impurities for controlling the lifetime of the carriers is composed of one element selected from the group consisting of gold, iron and copper.

Claim 11

A semiconductor switching device as claimed in claim 5, wherein the concentration of said impurities in said second central region has its maximum value at the portion adjacent to said central PN junction and decreases continuously toward said second end PN junction to exhibit its minimum value at the portion adjacent to said second end PN junction.

Claim 12

In a semiconductor switching device having a turn-off time characteristic and a forward voltage drop Characteristic: a semiconductor wafer having four opposed regions of alternate conductivity types collectively defining three p-n junctions wherein one of the regions defining the central junction is composed of material having a greater resistivity than that of the other region defining said central junction; and impurities in said wafer for controlling the lifetime of carriers injected therein during use of the semiconductor switching device and having an impurity concentration equal to a first value at said central junction thereby proportionally determining the turn-off time characteristic of the device and an impurity concentration equal to a second value at the outer junction partly defined by said one region thereby inversely determining the forward voltage drop characteristic of said device; and wherein said impurities are distributed in said wafer such that the impurity concentration increases from said outer junction to said central junction and said first value is greater than 1.2 times said second value thereby imparting to said device a faster turn-off time characteristic for an equivalent forward voltage drop characteristic with respect to a device with a substantially constant impurity concentration distribution and a lower forward voltage drop characteristic for an equivalent turn-off time characteristic with respect to a device with a substantially constant impurity concentration distribution.

Claim 13

In a semiconductor switching device having a turn-off time characteristic and a forward voltage drop Characteristic: a semiconductor wafer having four opposed regions of alternate conductivity types collectively defining three p-n junctions wherein one of the regions defining the central junction is composed of material having a greater resistivity than that of the other region defining said central junction; and impurities in said wafer for controlling the lifetime of carriers injected therein during use of the semiconductor switching device and having an impurity concentration equal to a first value at said central junction thereby proportionally determining the turn-off time characteristic of the device and an impurity concentration equal to a second value at the outer junction partly defined by said one region thereby inversely determining the forward voltage drop characteristic of said device; and wherein said impurities are distributed in said wafer such that the impurity concentration increases from said outer junction to said central junction and said first value is greater than 1.2 times said second value thereby imparting to said device a faster turn-off time characteristic for an equivalent forward voltage drop characteristic with respect to a device with a substantially constant impurity concentration distribution and a lower forward voltage drop characteristic for an equivalent turn-off time characteristic with respect to a device with a substantially constant impurity concentration distribution.

Claim 14

A semiconductor switching device according to claim 10, wherein said semiconductor wafer is substantially composed of silicon.

Claim 15

A semiconductor switching device according to claim 10, wherein said impurities are composed of one element selected from a group consisting of gold, iron and copper.