Process for wafer fabrication of high blocking voltage silicon elements

Claim 2

A process according to claim 2 in which the step of forming a stressed region is accomplished by mechanically abrading the epitaxial layer.

Claim 3

A process according to claim 2 in which the step of forming a stressed region is accomplished by substitutional diffusion with impurity atoms.

Claim 4

A process according to claim 1 in which the silicon wafer is heated in an oxidizing atmosphere.

Claim 5

A process according to claim 1 in which the silicon wafer is cooled after heating within a dry atmosphere.

Claim 6

A process according to claim 1 in which the junction lies between and contiguous with tHe first and second zones, the resistivity of the first zone is greater than that of the second zone, and the wafer is grooved by etching so that the junction intersections with the groove surfaces are positively beveled to increase the voltage-blocking capabilities of the silicon crystal elements.

Claim 7

A process according to claim 1 in which the wafer is grooved by etching to a depth so that the junction intercepts the groove surfaces adjacent the groove trough areas.

Claim 8

A process according to claim 1 in which the wafer is grooved by etching so that the groove trough areas are spaced from the epitaxial layer.

Claim 9

A process of forming from a single silicon crystal wafer a plurality of separate silicon crystal elements for use in thyristors comprising forming a silicon crystal wafer with an interrupted first zone adjacent a first major surface and a fourth zone adjacent an opposed major surface with second and third zones interposed between the first and fourth zones, the first and third zones being of a first conductivity type and the second and fourth zones being of an opposite conductivity type, the second zone extending to the first major surface through spaced interruptions in the first zone, the first and second zones forming a first junction therebetween, the second and third zones forming a second junction therebetween, and the third and fourth zones forming a third junction therebetween, epitaxially depositing onto the opposed major surface a layer having a conductivity type corresponding to that of the fourth zone and a thickness of at least 2 mils, grooving the silicon crystal wafer from the first major surface to a depth nearer the opposed major surface than the depletion layer of maximum width contemplated to be associated with the third junction so that the first, second and third zones and at least a portion of the fourth zone are divided into sectors while the epitaxial layer remains unitary, forming a passivation layer over the exterior surface of the silicon wafer including the groove surfaces intersecting the junction while the wafer is heated, gettering and removing fast diffusion impurities from the wafer, removing the passivation layer from a portion of the epitaxial layer and the first major surface, attaching ohmic contacts to the exposed silicon wafer surfaces, and subdividing the silicon crystal wafer through the epitaxial layer portion underlying the groove trough areas to form separately useable silicon crystal elements each including a sector of each zone.

Claim 10

A process according to claim 10 in which the gettering and removing of impurities is performed by forming a stressed region on a surface of the epitaxial layer of the silicon wafer, relieving stresses during heating to form crystal dislocations capable of acting as traps for fast diffusing impurities, and removing the impurity-containing region prior to attaching ohmic contacts.

Claim 11

A process according to claim 11 in which the step of forming a stressed region is accomplished by mechanically abrading the epitaxial layer.

Claim 12

A process according to claim 11 in which the step of forming a stressed region is accomplished by substitutional diffusion with impurity atoms.

Claim 13

A process according to claim 10 in which the silicon wafer is heated in an oxidizing atmosphere.

Claim 14

A process according to claim 10 in which the silicon wafer is cooled after heating within a dry atmosphere.

Claim 15

A process according to claim 10 in which the silicon wafer is grooved by etching from the first major surface to a depth adjacent the epitaxial layer to positively bevel the third junction.

Claim 16

A process according to claim 10 in which the silicon wafer is grooved by etching so that the third junction intercepts the grooves adjacent the trough areas.