US3728592A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor structure having reduced carrier lifetime
Assignee: International Business Machines Corp
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Filing: 1971-09-14
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Granted: 1973-04-17
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Expires: 1991-09-14
Abstract
Abstract A method of fabricating high-speed planar transistor structures by reducing carrier lifetime through doping with carrier lifetime killers. Gold is diffused through the front surface of the silicon structure during transistor fabrication. The gold is introduced from the vapor phase in a controlled manner so that its solid solubility in silicon is not exceeded. A simultaneous gold and base diffusion is preferred. Such a simultaneous diffusion produces a novel planar transistor structure having a gold distribution curve with an unexpected increased concentration peak in the region proximate to the basecollector junction.
Inventors
- 👤 M Joshi
- 👤 Hsing Yeh Tsu
- 👤 B Masters
- 👤 O Viva
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:18
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10P; H10P95/00; Y; Y10; Y10S; Y10S438/00; Y10S438/904
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
11 words
The planar transistor of claim 1 wherein said atoms are gold.
Claim 2
Dependent Claim
31 words
The planar transistor of claim 2 wherein the concentration at said peak is at least one order of magnitude greater than the minimum level to which the concentration is first decreased.
Claim 3
Dependent Claim
27 words
The planar transistor of claim 2 wherein the concentration at said peak is at least one order of magnitude greater than the concentration at the emitter-base junction.
Claim 4
Dependent Claim
14 words
The planar transistor of claim 2 wherein said peak is in the collector region.
Claim 5
Dependent Claim
11 words
The planar transistor of claim 2 wherein said substrate is silicon.
Claim 6
Dependent Claim
23 words
The planar transistor of claim 6 wherein said emitter and base regions are formed within an epitaxial layer carried on a silicon support.
Claim 7
Dependent Claim
38 words
The planar transistor of claim 7 further including a low resistivity buried subcollector region of the same conductivity type as the epitaxial region formed in the surface of said silicon support beneath the emitter and intrinsic base regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-16 | 1976-10-16 | 1977-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-16 | 1980-10-16 | 1981-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-16 | 1984-10-16 | 1985-04-17 | $7700.00 | Window Closed / Lapsed |