Patent US2364013A successfully refreshed from Google Patents.
US3662232A
Expired / Lapsed
US
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Semiconductor devices having low minority carrier lifetime and process for producing same
Assignee: FMC Corp
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Filing: 1970-12-10
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Granted: 1972-05-09
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Expires: 1990-12-10
Abstract
Abstract Silicon diodes and silicon controlled rectifiers are provided with reduced minority carrier lifetimes without a significant increase in forward voltage drop or reverse leakage current by means of a gadolinium dopant which is diffused into the semiconductor wafers after first being applied on one face thereof by means of a conventional sputtering process. Gadolinium is sputtered onto the base side of the rectifiers from a foil of the pure metal in a vacuum. The wafers are then placed in a furnace at a temperature above 820* C where the diffusion process takes place.
Inventors
- 👤 Donald F Stahr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:34
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10D62/834; H10D99/00; H10P; H10P95/00; Y; Y10; Y10S; Y10S438/00; Y10S438/904; Y10S438/914; Y10S438/917
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
29 words
In a process for making a semiconductor as set forth in claim 1 wherein said gadolinium is introduced by solid state diffusion through the base of said semiconductor device.
Claim 2
Dependent Claim
37 words
In a process for making a semiconductor as set forth in claim 2 including the step of sputtering the gadolinium onto one face of the semiconductor device prior to the diffusion of the gadolinium into the device.
Claim 3
Dependent Claim
20 words
In a process for making semiconductor as set forth in claim 1 wherein said semiconductor device is comprised of silicon.
Claim 4
Dependent Claim
80 words
In a process for making a silicon PN junction wafer including the steps of providing a silicon wafer and producing adjacent regions of opposite conductivity type respectively therein for forming a PN junction in said wafer, the improvement comprising the steps of applying a thin film of gadolinium to one face of the wafer, and heating the wafer for diffusing the gadolinium into the wafer and reducing the minority carrier lifetime in the space charge region of said PN junction.
Claim 5
Dependent Claim
26 words
In a process for making a silicon PN junction wafer according to claim 5 wherein said film of gadolinium is applied by a vacuum sputtering technique.
Claim 6
Dependent Claim
32 words
In a process for making a silicon PN junction wafer according to claim 6 wherein said diffusion process is carried out in a furnace at a temperature of at least 820* C.
Claim 7
Dependent Claim
32 words
In a process for making a silicon PN junction device according to claim 7 wherein said diffusion process is carried out for periods of from about 3 minutes to about 9 minutes.
Claim 8
Dependent Claim
46 words
A silicon rectifying device comprising a silicon body having at least one N-type region and at least one P-type region forming a PN junction in the body, the space charge region of said junction containing dopant inclusions of gadolinium for reducing the minority carrier lifetime therein.
Claim 9
Dependent Claim
13 words
A device according to claim 9 wherein said device comprises a silicon diode.
Claim 10
Dependent Claim
14 words
A device according to claim 9 wherein said device comprises a silicon controlled rectifier.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-09 | 1975-11-08 | 1976-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-09 | 1979-11-08 | 1980-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-09 | 1983-11-08 | 1984-05-09 | $7700.00 | Window Closed / Lapsed |